Commit 86fa0b98 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: Refactor DML21 Initialization and Configuration 



[Why & How]
- Consolidated the initialization of DML21 parameters into a single
function `dml21_populate_dml_init_params` to streamline the process
and improve code readability.
- Updated the function signatures in the header files to reflect changes
in parameter passing for DML context.
- Removed redundant debug option handling and integrated it into the new
configuration population function.
- Adjusted the DML21 initialization logic in the wrapper to accommodate
the new structure, ensuring compatibility with different DCN versions.
- Enhanced the handling of clock parameters and bounding box configurations
from various sources, including hardware defaults and software policies.
- Improved the clarity of the code by renaming functions and variables for
better understanding of their purposes.

Reviewed-by: default avatarAustin Zheng <austin.zheng@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8ebfc4d2

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+288 −224
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
//

// Copyright 2024 Advanced Micro Devices, Inc.





#include "dml21_wrapper.h"

#include "dml2_core_dcn4_calcs.h"

#include "dml2_internal_shared_types.h"
@@ -11,99 +10,92 @@ 
#include "dml21_translation_helper.h"

#include "bounding_boxes/dcn4_soc_bb.h"



static void dml21_apply_dmub_bb_params(struct dml2_soc_bb *soc_bb, const void *dmub_bb_params, const struct dc *in_dc)

{

	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_4_01:

	default:

		break;

	}

}



static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options,

		const struct dc *in_dc,

		const struct dml2_configuration_options *config)

{

	const struct dml2_soc_bb *soc_bb;

	const struct dml2_soc_qos_parameters *qos_params;



	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_4_01:

	default:

		soc_bb = &dml2_socbb_dcn401;



		qos_params = &dml_dcn4_variant_a_soc_qos_params;

	}

	bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable;



	/* patch soc bb */

	memcpy(&dml_init->soc_bb, soc_bb, sizeof(struct dml2_soc_bb));

	/* ODM options */

	pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;

	pmo_options->disable_dyn_odm_for_multi_stream = true;

	pmo_options->disable_dyn_odm_for_stream_with_svp = true;



	if (config->bb_from_dmub)

		dml21_apply_dmub_bb_params(&dml_init->soc_bb, config->bb_from_dmub, in_dc);

	pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1);



	/* patch qos params */

	memcpy(&dml_init->soc_bb.qos_parameters, qos_params, sizeof(struct dml2_soc_qos_parameters));

}



static void dml21_external_socbb_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config)

{

	memcpy(&dml_init->soc_bb, &config->external_socbb_ip_params->soc_bb, sizeof(struct dml2_soc_bb));

}

	/* NOTE: DRR and SubVP Require FAMS2 */

	pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||

			in_dc->debug.force_disable_subvp ||

			disable_fams2;

	pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||

			disable_fams2;

	pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||

			disable_fams2;

	pmo_options->disable_fams2 = disable_fams2;



static void dml21_external_ip_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config)

{

	memcpy(&dml_init->ip_caps, &config->external_socbb_ip_params->ip_params, sizeof(struct dml2_ip_capabilities));

	pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||

			in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;

	pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE;

}



static void dml21_init_ip_params(struct dml2_initialize_instance_in_out *dml_init,

/*

 * Populate dml_init based on default static values in soc bb. The default

 * values are for reference and support at least minimal operation of current

 * SoC and DCN hardware. The values could be modifed by subsequent override

 * functions to reflect our true hardware capability.

 */

static void populate_default_dml_init_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	const struct dml2_ip_capabilities *ip_caps;



	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_4_01:

		dml_init->options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp;

		dml21_populate_pmo_options(&dml_init->options.pmo_options, in_dc, config);

		dml_init->soc_bb = dml2_socbb_dcn401;

		dml_init->soc_bb.qos_parameters = dml_dcn4_variant_a_soc_qos_params;

		dml_init->ip_caps = dml2_dcn401_max_ip_caps;

		break;

	default:

		ip_caps = &dml2_dcn401_max_ip_caps;

		memset(dml_init, 0, sizeof(*dml_init));

		DC_ERR("unsupported dcn version for DML21!");

		return;

	}



	memcpy(&dml_init->ip_caps, ip_caps, sizeof(struct dml2_ip_capabilities));

}



void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_init,

static void override_dml_init_with_values_from_hardware_default(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	if (config->use_native_soc_bb_construction)

		dml21_init_socbb_params(dml_init, config, in_dc);

	else

		dml21_external_socbb_params(dml_init, config);

	dml_init->soc_bb.dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

	dml_init->soc_bb.dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000;

	dml_init->soc_bb.dispclk_dppclk_vco_speed_mhz = in_dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

}



void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init,

/*

 * SMU stands for System Management Unit. It is a power management processor.

 * It owns the initialization of dc's clock table and programming of clock values

 * based on dc's requests.

 * Our clock values in base soc bb is a dummy placeholder. The real clock values

 * are retrieved from SMU firmware to dc clock table at runtime.

 * This function overrides our dummy placeholder values with real values in dc

 * clock table.

 */

static void override_dml_init_with_values_from_smu(

		struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	if (config->use_native_soc_bb_construction)

		dml21_init_ip_params(dml_init, config, in_dc);

	else

		dml21_external_ip_params(dml_init, config);

}



void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config, const struct dc *in_dc)

{

	int i;



	const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params;

	const struct clk_limit_table *dc_clk_table = &dc_bw_params->clk_table;

	struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb;

	struct dml2_soc_state_table *dml_clk_table = &dml_soc_bb->clk_table;

	struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table;



	if (!in_dc->clk_mgr->funcs->is_smu_present ||

			!in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr))

		/* skip if smu is not present */

		return;



	/* override clocks if smu is present */

	if (in_dc->clk_mgr->funcs->is_smu_present && in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {

	/* dcfclk */

	if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {

		dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
@@ -264,33 +256,17 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in 
			}

		}

	}



		/* do not override phyclks for now */

		/* phyclk */

		// dml_clk_table->phyclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_levels;

		// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {

		// 	dml_clk_table->phyclk.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_mhz * 1000;

		// }



		/* phyclk_d18 */

		// dml_clk_table->phyclk_d18.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_d18_levels;

		// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {

		// 	dml_clk_table->phyclk_d18.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_d18_mhz * 1000;

		// }



		/* phyclk_d32 */

		// dml_clk_table->phyclk_d32.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_d32_levels;

		// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {

		// 	dml_clk_table->phyclk_d32.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_d32_mhz * 1000;

		// }

}



	dml_soc_bb->dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

	dml_soc_bb->dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000;

	dml_soc_bb->xtalclk_mhz = in_dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;

	dml_soc_bb->dispclk_dppclk_vco_speed_mhz = in_dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

static void override_dml_init_with_values_from_vbios(

		struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params;

	struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb;

	struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table;



	/* override bounding box paramters from VBIOS */

	if (in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns > 0)

		dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =

				(in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns + 9) / 10;
@@ -317,32 +293,120 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in 
		dml_clk_table->dram_config.channel_width_bytes = in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

	}



	/* override bounding box paramters from DC config */

	if (in_dc->bb_overrides.sr_exit_time_ns) {

		dml_soc_bb->power_management_parameters.stutter_exit_latency_us =

				in_dc->bb_overrides.sr_exit_time_ns / 1000.0;

	dml_init->soc_bb.xtalclk_mhz = in_dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;

}



	if (in_dc->bb_overrides.sr_enter_plus_exit_time_ns) {

		dml_soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us =

				in_dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;



static void override_dml_init_with_values_from_dmub(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	/*

	 * TODO - There seems to be overlaps between the values overriden from

	 * dmub and vbios. Investigate and identify the values that DMUB needs

	 * to own.

	 */

// 	const struct dmub_soc_bb_params *dmub_bb_params =

// 			(const struct dmub_soc_bb_params *)config->bb_from_dmub;



// 	if (dmub_bb_params == NULL)

// 		return;



// 	if (dmub_bb_params->dram_clk_change_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us =

// 			(double) dmub_bb_params->dram_clk_change_blackout_ns / 1000.0;

// 	if (dmub_bb_params->dram_clk_change_read_only_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.dram_clk_change_read_only_us =

// 			(double) dmub_bb_params->dram_clk_change_read_only_ns / 1000.0;

// 	if (dmub_bb_params->dram_clk_change_write_only_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.dram_clk_change_write_only_us =

// 			(double) dmub_bb_params->dram_clk_change_write_only_ns / 1000.0;

// 	if (dmub_bb_params->fclk_change_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us =

// 			(double) dmub_bb_params->fclk_change_blackout_ns / 1000.0;

// 	if (dmub_bb_params->g7_ppt_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.g7_ppt_blackout_us =

// 			(double) dmub_bb_params->g7_ppt_blackout_ns / 1000.0;

// 	if (dmub_bb_params->stutter_enter_plus_exit_latency_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us =

// 			(double) dmub_bb_params->stutter_enter_plus_exit_latency_ns / 1000.0;

// 	if (dmub_bb_params->stutter_exit_latency_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us =

// 			(double) dmub_bb_params->stutter_exit_latency_ns / 1000.0;

// 	if (dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.z8_stutter_enter_plus_exit_latency_us =

// 			(double) dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns / 1000.0;

// 	if (dmub_bb_params->z8_stutter_exit_latency_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.z8_stutter_exit_latency_us =

// 			(double) dmub_bb_params->z8_stutter_exit_latency_ns / 1000.0;

// 	if (dmub_bb_params->z8_min_idle_time_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.z8_min_idle_time =

// 			(double) dmub_bb_params->z8_min_idle_time_ns / 1000.0;

// #ifndef TRIM_DML2_DCN6B_IP_SENSITIVE

// 	if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.lpddr5_dram_clk_change_blackout_us =

// 			(double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0;

// 	if (dmub_bb_params->type_b_ppt_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.lpddr5_ppt_blackout_us =

// 			(double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0;

// #else

// 	if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.type_b_dram_clk_change_blackout_us =

// 			(double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0;

// 	if (dmub_bb_params->type_b_ppt_blackout_ns > 0)

// 		dml_init->soc_bb.power_management_parameters.type_b_ppt_blackout_us =

// 			(double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0;

// #endif

// 	if (dmub_bb_params->vmin_limit_dispclk_khz > 0)

// 		dml_init->soc_bb.vmin_limit.dispclk_khz = dmub_bb_params->vmin_limit_dispclk_khz;

// 	if (dmub_bb_params->vmin_limit_dcfclk_khz > 0)

// 		dml_init->soc_bb.vmin_limit.dcfclk_khz = dmub_bb_params->vmin_limit_dcfclk_khz;

//	if (dmub_bb_params->g7_temperature_read_blackout_ns > 0)

//		dml_init->soc_bb.power_management_parameters.g7_temperature_read_blackout_us =

//				(double) dmub_bb_params->g7_temperature_read_blackout_ns / 1000.0;

}



static void override_dml_init_with_values_from_software_policy(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	if (!config->use_native_soc_bb_construction) {

		dml_init->soc_bb = config->external_socbb_ip_params->soc_bb;

		dml_init->ip_caps = config->external_socbb_ip_params->ip_params;

	}



	if (in_dc->bb_overrides.dram_clock_change_latency_ns) {

		dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =

	if (in_dc->bb_overrides.sr_exit_time_ns)

		dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us =

				in_dc->bb_overrides.sr_exit_time_ns / 1000.0;



	if (in_dc->bb_overrides.sr_enter_plus_exit_time_ns)

		dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us =

				in_dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;



	if (in_dc->bb_overrides.dram_clock_change_latency_ns)

		dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us =

				in_dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

	}



	if (in_dc->bb_overrides.fclk_clock_change_latency_ns) {

		dml_soc_bb->power_management_parameters.fclk_change_blackout_us =

	if (in_dc->bb_overrides.fclk_clock_change_latency_ns)

		dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us =

				in_dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0;

}



	//TODO

	// if (in_dc->bb_overrides.dummy_clock_change_latency_ns) {

	// 	dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =

	// 			in_dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

	// }

void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init,

		const struct dml2_configuration_options *config,

		const struct dc *in_dc)

{

	populate_default_dml_init_params(dml_init, config, in_dc);



	override_dml_init_with_values_from_hardware_default(dml_init, config, in_dc);



	override_dml_init_with_values_from_smu(dml_init, config, in_dc);



	override_dml_init_with_values_from_vbios(dml_init, config, in_dc);



	override_dml_init_with_values_from_dmub(dml_init, config, in_dc);



	override_dml_init_with_values_from_software_policy(dml_init, config, in_dc);

}



static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

+1 −3
Original line number Diff line number Diff line
@@ -17,9 +17,7 @@ struct dml2_context; 
struct dml2_configuration_options;

struct dml2_initialize_instance_in_out;



void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

+11 −47
Original line number Diff line number Diff line
@@ -35,15 +35,11 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) 
	return true;

}



static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

static void dml21_populate_configuration_options(const struct dc *in_dc,

		struct dml2_context *dml_ctx,

		const struct dml2_configuration_options *config)

{

	bool disable_fams2;

	struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options;



	/* ODM options */

	pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;

	pmo_options->disable_dyn_odm_for_multi_stream = true;

	pmo_options->disable_dyn_odm_for_stream_with_svp = true;

	dml_ctx->config = *config;



	/* UCLK P-State options */

	if (in_dc->debug.dml21_force_pstate_method) {
@@ -53,52 +49,20 @@ static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_contex 
	} else {

		dml_ctx->config.pmo.force_pstate_method_enable = false;

	}



	pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1);



	/* NOTE: DRR and SubVP Require FAMS2 */

	disable_fams2 = !in_dc->debug.fams2_config.bits.enable;

	pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||

			in_dc->debug.force_disable_subvp ||

			disable_fams2;

	pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||

			disable_fams2;

	pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||

			disable_fams2;

	pmo_options->disable_fams2 = disable_fams2;



	pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||

			in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;

	pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE;

}



static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

{

	switch (in_dc->ctx->dce_version) {

	case DCN_VERSION_4_01:

		(*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp;

		break;

	default:

		(*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid;

	}



	(*dml_ctx)->architecture = dml2_architecture_21;

	dml_ctx->architecture = dml2_architecture_21;



	/* Store configuration options */

	(*dml_ctx)->config = *config;

	dml21_populate_configuration_options(in_dc, dml_ctx, config);



	DC_FP_START();



	/*Initialize SOCBB and DCNIP params */

	dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc);

	dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc);

	dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc);



	/* apply debug overrides */

	dml21_apply_debug_options(in_dc, *dml_ctx, config);

	dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, config, in_dc);



	/*Initialize DML21 instance */

	dml2_initialize_instance(&(*dml_ctx)->v21.dml_init);

	dml2_initialize_instance(&dml_ctx->v21.dml_init);



	DC_FP_END();

}
@@ -109,7 +73,7 @@ bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const s 
	if (!dml21_allocate_memory(dml_ctx))

		return false;



	dml21_init(in_dc, dml_ctx, config);

	dml21_init(in_dc, *dml_ctx, config);



	return true;

}
@@ -495,7 +459,7 @@ bool dml21_create_copy(struct dml2_context **dst_dml_ctx, 
	return true;

}



void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

{

	dml21_init(in_dc, dml_ctx, config);

}

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ void dml21_copy(struct dml2_context *dst_dml_ctx, 
	struct dml2_context *src_dml_ctx);

bool dml21_create_copy(struct dml2_context **dst_dml_ctx,

	struct dml2_context *src_dml_ctx);

void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);



/**

 * dml21_validate - Determines if a display configuration is supported or not.

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

+5 −7
Original line number Diff line number Diff line
@@ -580,8 +580,8 @@ static inline struct dml2_context *dml2_allocate_memory(void) 


static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

{

	if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) {

		dml21_reinit(in_dc, dml2, config);

	if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {

		dml21_reinit(in_dc, *dml2, config);

		return;

	}
@@ -626,9 +626,7 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op 
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

{

	// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.

	if ((in_dc->debug.using_dml21)

			&& (in_dc->ctx->dce_version == DCN_VERSION_4_01

		))

	if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01))

		return dml21_create(in_dc, dml2, config);



	// Allocate Mode Lib Ctx
@@ -697,8 +695,8 @@ void dml2_reinit(const struct dc *in_dc, 
				 const struct dml2_configuration_options *config,

				 struct dml2_context **dml2)

{

	if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) {

		dml21_reinit(in_dc, dml2, config);

	if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {

		dml21_reinit(in_dc, *dml2, config);

		return;

	}