Commit 875d742c authored by Radu Rendec's avatar Radu Rendec Committed by Will Deacon
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arm64: cacheinfo: Avoid out-of-bounds write to cacheinfo array 



The loop that detects/populates cache information already has a bounds
check on the array size but does not account for cache levels with
separate data/instructions cache. Fix this by incrementing the index
for any populated leaf (instead of any populated level).

Fixes: 5d425c18 ("arm64: kernel: add support for cpu cache information")

Signed-off-by: default avatarRadu Rendec <rrendec@redhat.com>
Link: https://lore.kernel.org/r/20250206174420.2178724-1-rrendec@redhat.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ca0f4fe7

arch/arm64/kernel/cacheinfo.c

+7 −5
Original line number Diff line number Diff line
@@ -101,16 +101,18 @@ int populate_cache_leaves(unsigned int cpu) 
	unsigned int level, idx;

	enum cache_type type;

	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct cacheinfo *this_leaf = this_cpu_ci->info_list;

	struct cacheinfo *infos = this_cpu_ci->info_list;



	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&

	     idx < this_cpu_ci->num_leaves; idx++, level++) {

	     idx < this_cpu_ci->num_leaves; level++) {

		type = get_cache_type(level);

		if (type == CACHE_TYPE_SEPARATE) {

			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);

			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);

			if (idx + 1 >= this_cpu_ci->num_leaves)

				break;

			ci_leaf_init(&infos[idx++], CACHE_TYPE_DATA, level);

			ci_leaf_init(&infos[idx++], CACHE_TYPE_INST, level);

		} else {

			ci_leaf_init(this_leaf++, type, level);

			ci_leaf_init(&infos[idx++], type, level);

		}

	}

	return 0;