Commit 8774029f authored by Qingqing Zhuo's avatar Qingqing Zhuo Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN35 CLK_MGR 



[Why & How]
Add CLK_MGR handling for DCN35.

v2: Drop stale SMU interfaces (Alex)

Signed-off-by: default avatarQingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6f8b7565

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −0
Original line number Diff line number Diff line
@@ -1680,6 +1680,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 


	init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];

	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];

	init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];



	INIT_LIST_HEAD(&adev->dm.da_list);

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+8 −0
Original line number Diff line number Diff line
@@ -172,4 +172,12 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC 


AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)



###############################################################################

# DCN35

###############################################################################

CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o



AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)

endif

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 
#include "dcn315/dcn315_clk_mgr.h"

#include "dcn316/dcn316_clk_mgr.h"

#include "dcn32/dcn32_clk_mgr.h"

#include "dcn35/dcn35_clk_mgr.h"



int clk_mgr_helper_get_active_display_cnt(

		struct dc *dc,
@@ -405,6 +406,10 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) 
		dcn314_clk_mgr_destroy(clk_mgr);

		break;



	case AMDGPU_FAMILY_GC_11_5_0:

		dcn35_clk_mgr_destroy(clk_mgr);

		break;



	default:

		break;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

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+1001 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

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+63 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DCN35_CLK_MGR_H__

#define __DCN35_CLK_MGR_H__

#include "clk_mgr_internal.h"



#define NUM_CLOCK_SOURCES   5



struct dcn35_watermarks;



struct dcn35_smu_watermark_set {

	struct dcn35_watermarks *wm_set;

	union large_integer mc_address;

};



struct dcn35_ss_info_table {

	uint32_t ss_divider;

	uint32_t ss_percentage[NUM_CLOCK_SOURCES];

};



struct clk_mgr_dcn35 {

	struct clk_mgr_internal base;

	struct dcn35_smu_watermark_set smu_wm_set;

};



bool dcn35_are_clock_states_equal(struct dc_clocks *a,

		struct dc_clocks *b);

void dcn35_init_clocks(struct clk_mgr *clk_mgr);

void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,

			struct dc_state *context,

			bool safe_to_lower);



void dcn35_clk_mgr_construct(struct dc_context *ctx,

		struct clk_mgr_dcn35 *clk_mgr,

		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg);



void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);



#endif //__DCN35_CLK_MGR_H__