Commit 87781880 authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD)
Browse files

x86/bugs: Add SRSO_USER_KERNEL_NO support



If the machine has:

  CPUID Fn8000_0021_EAX[30] (SRSO_USER_KERNEL_NO) -- If this bit is 1,
  it indicates the CPU is not subject to the SRSO vulnerability across
  user/kernel boundaries.

have it fall back to IBPB on VMEXIT only, in the case it is going to run
VMs:

  Speculative Return Stack Overflow: Mitigation: IBPB on VMEXIT only

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarNikolay Borisov <nik.borisov@suse.com>
Link: https://lore.kernel.org/r/20241202120416.6054-2-bp@kernel.org
parent fc033cf2
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+1 −0
Original line number Diff line number Diff line
@@ -465,6 +465,7 @@
#define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
#define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */
#define X86_FEATURE_SRSO_USER_KERNEL_NO	(20*32+30) /* CPU is not affected by SRSO across user/kernel boundaries */

/*
 * Extended auxiliary flags: Linux defined - for features scattered in various
+4 −0
Original line number Diff line number Diff line
@@ -2615,6 +2615,9 @@ static void __init srso_select_mitigation(void)
		break;

	case SRSO_CMD_SAFE_RET:
		if (boot_cpu_has(X86_FEATURE_SRSO_USER_KERNEL_NO))
			goto ibpb_on_vmexit;

		if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) {
			/*
			 * Enable the return thunk for generated code
@@ -2658,6 +2661,7 @@ static void __init srso_select_mitigation(void)
		}
		break;

ibpb_on_vmexit:
	case SRSO_CMD_IBPB_ON_VMEXIT:
		if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) {
			if (!boot_cpu_has(X86_FEATURE_ENTRY_IBPB) && has_microcode) {
+1 −0
Original line number Diff line number Diff line
@@ -1270,6 +1270,7 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
	VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
	VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
	VULNBL_AMD(0x19, SRSO),
	VULNBL_AMD(0x1a, SRSO),
	{}
};