perf vendor events: Update broadwellx metrics add event counter information (87835d9f) · Commits · git / linux-net

tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json

+46 −82

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tools/perf/pmu-events/arch/x86/broadwellx/cache.json

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tools/perf/pmu-events/arch/x86/broadwellx/counter.json

0 → 100644

+57 −0

Original line number	Diff line number	Diff line
		[
		{
		"Unit": "core",
		"CountersNumFixed": "3",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "CBOX",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "HA",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "IRP",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "2"
		},
		{
		"Unit": "PCU",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "QPI",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "R2PCIe",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "R3QPI",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "3"
		},
		{
		"Unit": "SBOX",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "UBOX",
		"CountersNumFixed": "1",
		"CountersNumGeneric": "2"
		},
		{
		"Unit": "iMC",
		"CountersNumFixed": "1",
		"CountersNumGeneric": "4"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json

+22 −0

Original line number	Diff line number	Diff line
		[
		{
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
		"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -9,6 +10,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
		"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -17,6 +19,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
		"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -25,6 +28,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
		"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -33,6 +37,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
		"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -41,6 +46,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
		"SampleAfterValue": "2000006",
		@@ -48,6 +54,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.PACKED",
		"SampleAfterValue": "2000004",
		@@ -55,6 +62,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
		"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -63,6 +71,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
		"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -71,6 +80,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
		"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -79,6 +89,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
		"SampleAfterValue": "2000005",
		@@ -86,6 +97,7 @@
		},
		{
		"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
		"Counter": "0,1,2,3",
		"EventCode": "0xc7",
		"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
		"SampleAfterValue": "2000003",
		@@ -93,6 +105,7 @@
		},
		{
		"BriefDescription": "Cycles with any input/output SSE or FP assist",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.ANY",
		@@ -102,6 +115,7 @@
		},
		{
		"BriefDescription": "Number of SIMD FP assists due to input values",
		"Counter": "0,1,2,3",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.SIMD_INPUT",
		"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
		@@ -110,6 +124,7 @@
		},
		{
		"BriefDescription": "Number of SIMD FP assists due to Output values",
		"Counter": "0,1,2,3",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.SIMD_OUTPUT",
		"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
		@@ -118,6 +133,7 @@
		},
		{
		"BriefDescription": "Number of X87 assists due to input value.",
		"Counter": "0,1,2,3",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.X87_INPUT",
		"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
		@@ -126,6 +142,7 @@
		},
		{
		"BriefDescription": "Number of X87 assists due to output value.",
		"Counter": "0,1,2,3",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.X87_OUTPUT",
		"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
		@@ -134,6 +151,7 @@
		},
		{
		"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
		"Counter": "0,1,2,3",
		"EventCode": "0x58",
		"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
		"SampleAfterValue": "1000003",
		@@ -141,6 +159,7 @@
		},
		{
		"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
		"Counter": "0,1,2,3",
		"EventCode": "0x58",
		"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
		"SampleAfterValue": "1000003",
		@@ -148,6 +167,7 @@
		},
		{
		"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
		"Counter": "0,1,2,3",
		"Errata": "BDM30",
		"EventCode": "0xC1",
		"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
		@@ -157,6 +177,7 @@
		},
		{
		"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
		"Counter": "0,1,2,3",
		"Errata": "BDM30",
		"EventCode": "0xC1",
		"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
		@@ -166,6 +187,7 @@
		},
		{
		"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
		"Counter": "0,1,2,3",
		"EventCode": "0xA0",
		"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
		"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD, VFMADDSUB, VFMSUB, VMSUBADD, VFNMADD, VFNMSUB. See the Broadwell Optimization Guide for more information.",

tools/perf/pmu-events/arch/x86/broadwellx/frontend.json

+28 −0

Original line number	Diff line number	Diff line
		[
		{
		"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
		"Counter": "0,1,2,3",
		"EventCode": "0xe6",
		"EventName": "BACLEARS.ANY",
		"SampleAfterValue": "100003",
		@@ -8,6 +9,7 @@
		},
		{
		"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
		"Counter": "0,1,2,3",
		"EventCode": "0xAB",
		"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
		"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
		@@ -16,6 +18,7 @@
		},
		{
		"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
		"Counter": "0,1,2,3",
		"EventCode": "0x80",
		"EventName": "ICACHE.HIT",
		"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
		@@ -24,6 +27,7 @@
		},
		{
		"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0x80",
		"EventName": "ICACHE.IFDATA_STALL",
		"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
		@@ -32,6 +36,7 @@
		},
		{
		"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
		"Counter": "0,1,2,3",
		"EventCode": "0x80",
		"EventName": "ICACHE.MISSES",
		"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
		@@ -40,6 +45,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
		@@ -49,6 +55,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
		@@ -58,6 +65,7 @@
		},
		{
		"BriefDescription": "Cycles MITE is delivering 4 Uops",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
		@@ -67,6 +75,7 @@
		},
		{
		"BriefDescription": "Cycles MITE is delivering any Uop",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
		@@ -76,6 +85,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_CYCLES",
		@@ -85,6 +95,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_UOPS",
		"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
		@@ -93,6 +104,7 @@
		},
		{
		"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.EMPTY",
		"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
		@@ -101,6 +113,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MITE_ALL_UOPS",
		"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
		@@ -109,6 +122,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MITE_CYCLES",
		@@ -118,6 +132,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MITE_UOPS",
		"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
		@@ -126,6 +141,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_CYCLES",
		@@ -135,6 +151,7 @@
		},
		{
		"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_DSB_CYCLES",
		@@ -144,6 +161,7 @@
		},
		{
		"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EdgeDetect": "1",
		"EventCode": "0x79",
		@@ -154,6 +172,7 @@
		},
		{
		"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_DSB_UOPS",
		"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
		@@ -162,6 +181,7 @@
		},
		{
		"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_MITE_UOPS",
		"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
		@@ -170,6 +190,7 @@
		},
		{
		"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EdgeDetect": "1",
		"EventCode": "0x79",
		@@ -179,6 +200,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_UOPS",
		"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
		@@ -187,6 +209,7 @@
		},
		{
		"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
		"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
		@@ -195,6 +218,7 @@
		},
		{
		"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
		@@ -204,6 +228,7 @@
		},
		{
		"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
		@@ -213,6 +238,7 @@
		},
		{
		"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"CounterMask": "3",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
		@@ -222,6 +248,7 @@
		},
		{
		"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
		"Counter": "0,1,2,3",
		"CounterMask": "2",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
		@@ -230,6 +257,7 @@
		},
		{
		"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",