Unverified Commit 87e12876 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-drivers-5.17' of... 

Merge tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers

i.MX drivers update for 5.17:

- A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver
  to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add
  i.MX8MN display related domain support.
- Add optional continuous burst clock support for imx-weim bus driver.
- Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in
  gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and
  MIX domain.

* tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
  dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
  soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
  soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
  bus: imx-weim: optionally enable continuous burst clock
  soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active
  soc: imx: gpcv2: Synchronously suspend MIX domains

Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a904c5f0 7f511d51

drivers/bus/imx-weim.c

+16 −2
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ struct imx_weim_devtype { 
	unsigned int	cs_stride;

	unsigned int	wcr_offset;

	unsigned int	wcr_bcm;

	unsigned int	wcr_cont_bclk;

};



static const struct imx_weim_devtype imx1_weim_devtype = {
@@ -41,6 +42,7 @@ static const struct imx_weim_devtype imx50_weim_devtype = { 
	.cs_stride	= 0x18,

	.wcr_offset	= 0x90,

	.wcr_bcm	= BIT(0),

	.wcr_cont_bclk	= BIT(3),

};



static const struct imx_weim_devtype imx51_weim_devtype = {
@@ -206,8 +208,20 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) 
	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {

		if (devtype->wcr_bcm) {

			reg = readl(base + devtype->wcr_offset);

			writel(reg | devtype->wcr_bcm,

				base + devtype->wcr_offset);

			reg |= devtype->wcr_bcm;



			if (of_property_read_bool(pdev->dev.of_node,

						"fsl,continuous-burst-clk")) {

				if (devtype->wcr_cont_bclk) {

					reg |= devtype->wcr_cont_bclk;

				} else {

					dev_err(&pdev->dev,

						"continuous burst clk not supported.\n");

					return -EINVAL;

				}

			}



			writel(reg, base + devtype->wcr_offset);

		} else {

			dev_err(&pdev->dev, "burst clk mode not supported.\n");

			return -EINVAL;

drivers/soc/imx/gpcv2.c

+28 −1
Original line number Diff line number Diff line
@@ -377,7 +377,7 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) 
		}

	}



	pm_runtime_put(domain->dev);

	pm_runtime_put_sync_suspend(domain->dev);



	return 0;
@@ -734,6 +734,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { 
			.map = IMX8MM_VPUH1_A53_DOMAIN,

		},

		.pgc   = BIT(IMX8MM_PGC_VPUH1),

		.keep_clocks = true,

	},



	[IMX8MM_POWER_DOMAIN_DISPMIX] = {
@@ -840,6 +841,32 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { 
			.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,

		},

		.pgc   = BIT(IMX8MN_PGC_GPUMIX),

		.keep_clocks = true,

	},



	[IMX8MN_POWER_DOMAIN_DISPMIX] = {

		.genpd = {

			.name = "dispmix",

		},

			.bits  = {

			.pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,

			.map = IMX8MN_DISPMIX_A53_DOMAIN,

			.hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,

			.hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,

		},

		.pgc   = BIT(IMX8MN_PGC_DISPMIX),

		.keep_clocks = true,

	},



	[IMX8MN_POWER_DOMAIN_MIPI] = {

		.genpd = {

			.name = "mipi",

		},

			.bits  = {

			.pxx = IMX8MN_MIPI_SW_Pxx_REQ,

			.map = IMX8MN_MIPI_A53_DOMAIN,

		},

		.pgc   = BIT(IMX8MN_PGC_MIPI),

	},

};

drivers/soc/imx/imx8m-blk-ctrl.c

+76 −1
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/clk.h>



#include <dt-bindings/power/imx8mm-power.h>

#include <dt-bindings/power/imx8mn-power.h>



#define BLK_SFT_RSTN	0x0

#define BLK_CLK_EN	0x4
@@ -498,6 +499,77 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { 
	.num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),

};





static int imx8mn_disp_power_notifier(struct notifier_block *nb,

				      unsigned long action, void *data)

{

	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,

						 power_nb);



	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)

		return NOTIFY_OK;



	/* Enable bus clock and deassert bus reset */

	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));

	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));



	/*

	 * On power up we have no software backchannel to the GPC to

	 * wait for the ADB handshake to happen, so we just delay for a

	 * bit. On power down the GPC driver waits for the handshake.

	 */

	if (action == GENPD_NOTIFY_ON)

		udelay(5);





	return NOTIFY_OK;

}



static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {

	[IMX8MN_DISPBLK_PD_MIPI_DSI] = {

		.name = "dispblk-mipi-dsi",

		.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },

		.num_clks = 2,

		.gpc_name = "mipi-dsi",

		.rst_mask = BIT(0) | BIT(1),

		.clk_mask = BIT(0) | BIT(1),

		.mipi_phy_rst_mask = BIT(17),

	},

	[IMX8MN_DISPBLK_PD_MIPI_CSI] = {

		.name = "dispblk-mipi-csi",

		.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },

		.num_clks = 2,

		.gpc_name = "mipi-csi",

		.rst_mask = BIT(2) | BIT(3),

		.clk_mask = BIT(2) | BIT(3),

		.mipi_phy_rst_mask = BIT(16),

	},

	[IMX8MN_DISPBLK_PD_LCDIF] = {

		.name = "dispblk-lcdif",

		.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },

		.num_clks = 3,

		.gpc_name = "lcdif",

		.rst_mask = BIT(4) | BIT(5),

		.clk_mask = BIT(4) | BIT(5),

	},

	[IMX8MN_DISPBLK_PD_ISI] = {

		.name = "dispblk-isi",

		.clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",

						"disp_apb_root"},

		.num_clks = 4,

		.gpc_name = "isi",

		.rst_mask = BIT(6) | BIT(7),

		.clk_mask = BIT(6) | BIT(7),

	},

};



static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {

	.max_reg = 0x84,

	.power_notifier_fn = imx8mn_disp_power_notifier,

	.domains = imx8mn_disp_blk_ctl_domain_data,

	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),

};



static const struct of_device_id imx8m_blk_ctrl_of_match[] = {

	{

		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
@@ -505,6 +577,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { 
	}, {

		.compatible = "fsl,imx8mm-disp-blk-ctrl",

		.data = &imx8mm_disp_blk_ctl_dev_data

	}, {

		.compatible = "fsl,imx8mn-disp-blk-ctrl",

		.data = &imx8mn_disp_blk_ctl_dev_data

	}, {

		/* Sentinel */

	}

include/dt-bindings/power/imx8mn-power.h

+5 −0
Original line number Diff line number Diff line
@@ -12,4 +12,9 @@ 
#define IMX8MN_POWER_DOMAIN_DISPMIX	3

#define IMX8MN_POWER_DOMAIN_MIPI	4



#define IMX8MN_DISPBLK_PD_MIPI_DSI	0

#define IMX8MN_DISPBLK_PD_MIPI_CSI	1

#define IMX8MN_DISPBLK_PD_LCDIF	2

#define IMX8MN_DISPBLK_PD_ISI	3



#endif