Commit 880932e6 authored by Pierre Gondois's avatar Pierre Gondois Committed by Vignesh Raghavendra
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arm64: dts: Update cache properties for ti 



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com
parent c48ac0ef

arch/arm64/boot/dts/ti/k3-am625.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ opp-1250000000 { 


	L2_0: l2-cache0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

		cache-size = <0x40000>;

		cache-line-size = <64>;

arch/arm64/boot/dts/ti/k3-am62a7.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ cpu3: cpu@3 { 


	L2_0: l2-cache0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

		cache-size = <0x40000>;

		cache-line-size = <64>;

arch/arm64/boot/dts/ti/k3-am642.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ cpu1: cpu@1 { 
	L2_0: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

		cache-unified;

		cache-size = <0x40000>;

		cache-line-size = <64>;

		cache-sets = <256>;

arch/arm64/boot/dts/ti/k3-am654.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ cpu3: cpu@101 { 
	L2_0: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

		cache-unified;

		cache-size = <0x80000>;

		cache-line-size = <64>;

		cache-sets = <512>;
@@ -102,6 +103,7 @@ L2_0: l2-cache0 { 
	L2_1: l2-cache1 {

		compatible = "cache";

		cache-level = <2>;

		cache-unified;

		cache-size = <0x80000>;

		cache-line-size = <64>;

		cache-sets = <512>;

arch/arm64/boot/dts/ti/k3-j7200.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ cpu1: cpu@1 { 
	L2_0: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

		cache-unified;

		cache-size = <0x100000>;

		cache-line-size = <64>;

		cache-sets = <1024>;