ASoC: dt-bindings: fsl-esai: Convert fsl,esai.txt to yaml

Freescale Enhanced Serial Audio Interface (ESAI) Controller

The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port

for serial communication with a variety of serial devices, including industry

standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and

other DSPs. It has up to six transmitters and four receivers.

Required properties:

  - compatible		: Compatible list, should contain one of the following

			  compatibles:

			  "fsl,imx35-esai",

			  "fsl,vf610-esai",

			  "fsl,imx6ull-esai",

			  "fsl,imx8qm-esai",

  - reg			: Offset and length of the register set for the device.

  - interrupts		: Contains the spdif interrupt.

  - dmas		: Generic dma devicetree binding as described in

			  Documentation/devicetree/bindings/dma/dma.txt.

  - dma-names		: Two dmas have to be defined, "tx" and "rx".

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:

	"core"		  The core clock used to access registers

	"extal"		  The esai baud clock for esai controller used to

			  derive HCK, SCK and FS.

	"fsys"		  The system clock derived from ahb clock used to

			  derive HCK, SCK and FS.

	"spba"		  The spba clock is required when ESAI is placed as a

			  bus slave of the Shared Peripheral Bus and when two

			  or more bus masters (CPU, DMA or DSP) try to access

			  it. This property is optional depending on the SoC

			  design.

  - fsl,fifo-depth	: The number of elements in the transmit and receive

			  FIFOs. This number is the maximum allowed value for

			  TFCR[TFWM] or RFCR[RFWM].

  - fsl,esai-synchronous: This is a boolean property. If present, indicating

			  that ESAI would work in the synchronous mode, which

			  means all the settings for Receiving would be

			  duplicated from Transmission related registers.

Optional properties:

  - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example:

esai: esai@2024000 {

	compatible = "fsl,imx35-esai";

	reg = <0x02024000 0x4000>;

	interrupts = <0 51 0x04>;

	clocks = <&clks 208>, <&clks 118>, <&clks 208>;

	clock-names = "core", "extal", "fsys";

	dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;

	dma-names = "rx", "tx";

	fsl,fifo-depth = <128>;

	fsl,esai-synchronous;

	big-endian;

};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/sound/fsl,esai.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Enhanced Serial Audio Interface (ESAI) Controller

maintainers:

  - Shengjiu Wang <shengjiu.wang@nxp.com>

  - Frank Li <Frank.Li@nxp.com>

description:

  The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port

  for serial communication with a variety of serial devices, including industry

  standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and

  other DSPs. It has up to six transmitters and four receivers.

properties:

  compatible:

    enum:

      - fsl,imx35-esai

      - fsl,imx6ull-esai

      - fsl,imx8qm-esai

      - fsl,vf610-esai

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  clocks:

    minItems: 3

    items:

      - description:

          The core clock used to access registers.

      - description:

          The esai baud clock for esai controller used to

          derive HCK, SCK and FS.

      - description:

          The system clock derived from ahb clock used to

          derive HCK, SCK and FS.

      - description:

          The spba clock is required when ESAI is placed as a

          bus slave of the Shared Peripheral Bus and when two

          or more bus masters (CPU, DMA or DSP) try to access

          it. This property is optional depending on the SoC

          design.

  clock-names:

    minItems: 3

    items:

      - const: core

      - const: extal

      - const: fsys

      - const: spba

  dmas:

    minItems: 2

    maxItems: 2

  dma-names:

    items:

      - const: rx

      - const: tx

  fsl,fifo-depth:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      The number of elements in the transmit and receive

      FIFOs. This number is the maximum allowed value for

      TFCR[TFWM] or RFCR[RFWM].

  fsl,esai-synchronous:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      This is a boolean property. If present, indicating

      that ESAI would work in the synchronous mode, which

      means all the settings for Receiving would be

      duplicated from Transmission related registers.

  big-endian:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      If this property is absent, the native endian mode

      will be in use as default, or the big endian mode

      will be in use for all the device registers.

required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - dmas

  - dma-names

  - fsl,fifo-depth

  - fsl,esai-synchronous

unevaluatedProperties: false

examples:

  - |

    esai@2024000 {

      compatible = "fsl,imx35-esai";

      reg = <0x02024000 0x4000>;

      interrupts = <0 51 0x04>;

      clocks = <&clks 208>, <&clks 118>, <&clks 208>;

      clock-names = "core", "extal", "fsys";

      dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;

      dma-names = "rx", "tx";

      fsl,fifo-depth = <128>;

      fsl,esai-synchronous;

      big-endian;

    };