dt-bindings: ethernet: eswin: Document for EIC7700 SoC

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Eswin EIC7700 SOC Eth Controller

maintainers:

  - Shuang Liang <liangshuang@eswincomputing.com>

  - Zhi Li <lizhi2@eswincomputing.com>

  - Shangjuan Wei <weishangjuan@eswincomputing.com>

description:

  Platform glue layer implementation for STMMAC Ethernet driver.

select:

  properties:

    compatible:

      contains:

        enum:

          - eswin,eic7700-qos-eth

  required:

    - compatible

allOf:

  - $ref: snps,dwmac.yaml#

properties:

  compatible:

    items:

      - const: eswin,eic7700-qos-eth

      - const: snps,dwmac-5.20

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  interrupt-names:

    const: macirq

  clocks:

    items:

      - description: AXI clock

      - description: Configuration clock

      - description: GMAC main clock

      - description: Tx clock

  clock-names:

    items:

      - const: axi

      - const: cfg

      - const: stmmaceth

      - const: tx

  resets:

    maxItems: 1

  reset-names:

    items:

      - const: stmmaceth

  rx-internal-delay-ps:

    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]

  tx-internal-delay-ps:

    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]

  eswin,hsp-sp-csr:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - description: Phandle to HSP(High-Speed Peripheral) device

      - description: Offset of phy control register for internal

                     or external clock selection

      - description: Offset of AXI clock controller Low-Power request

                     register

      - description: Offset of register controlling TX/RX clock delay

    description: |

      High-Speed Peripheral device needed to configure clock selection,

      clock low-power mode and clock delay.

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - phy-mode

  - resets

  - reset-names

  - rx-internal-delay-ps

  - tx-internal-delay-ps

  - eswin,hsp-sp-csr

unevaluatedProperties: false

examples:

  - |

    ethernet@50400000 {

        compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";

        reg = <0x50400000 0x10000>;

        clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,

                <&d0_clock 193>;

        clock-names = "axi", "cfg", "stmmaceth", "tx";

        interrupt-parent = <&plic>;

        interrupts = <61>;

        interrupt-names = "macirq";

        phy-mode = "rgmii-id";

        phy-handle = <&phy0>;

        resets = <&reset 95>;

        reset-names = "stmmaceth";

        rx-internal-delay-ps = <200>;

        tx-internal-delay-ps = <200>;

        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;

        snps,axi-config = <&stmmac_axi_setup>;

        snps,aal;

        snps,fixed-burst;

        snps,tso;

        stmmac_axi_setup: stmmac-axi-config {

            snps,blen = <0 0 0 0 16 8 4>;

            snps,rd_osr_lmt = <2>;

            snps,wr_osr_lmt = <2>;

        };

    };