Commit 8893a6bf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2024-01-15-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This is just a wrap up of fixes from the last few days. It has the
  proper fix to the i915/xe collision, we can clean up what you did
  later once rc1 lands.

  Otherwise it's a few other i915, a v3d, rockchip and a nouveau fix to
  make GSP load on some original Turing GPUs.

  i915:
   - Fixes for kernel-doc warnings enforced in linux-next
   - Another build warning fix for string formatting of intel_wakeref_t
   - Display fixes for DP DSC BPC and C20 PLL state verification

  v3d:
   - register readout fix

  rockchip:
   - two build warning fixes

  nouveau:
   - fix GSP loading on Turing with different nvdec configuration"

* tag 'drm-next-2024-01-15-1' of git://anongit.freedesktop.org/drm/drm:
  nouveau/gsp: handle engines in runl without nonstall interrupts.
  drm/i915/perf: reconcile Excess struct member kernel-doc warnings
  drm/i915/guc: reconcile Excess struct member kernel-doc warnings
  drm/i915/gt: reconcile Excess struct member kernel-doc warnings
  drm/i915/gem: reconcile Excess struct member kernel-doc warnings
  drm/i915/dp: Fix the max DSC bpc supported by source
  drm/i915: don't make assumptions about intel_wakeref_t type
  drm/i915/dp: Fix the PSR debugfs entries wrt. MST connectors
  drm/i915/display: Fix C20 pll selection for state verification
  drm/v3d: Fix support for register debugging on the RPi 4
  drm/rockchip: vop2: Drop unused if_dclk_rate variable
  drm/rockchip: vop2: Drop superfluous include
parents d8e6ba02 205e18c1

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+15 −10
Original line number Diff line number Diff line
@@ -3067,24 +3067,29 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, 
{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20;

	bool use_mplla;

	bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB;

	bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;

	int i;



	use_mplla = intel_c20_use_mplla(mpll_hw_state->clock);

	if (use_mplla) {

		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {

			I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],

					"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",

					crtc->base.base.id, crtc->base.name, i,

					mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);

		}

	} else {

	I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,

			"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",

			crtc->base.base.id, crtc->base.name,

			sw_use_mpllb, hw_use_mpllb);



	if (hw_use_mpllb) {

		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {

			I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],

					"[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",

					crtc->base.base.id, crtc->base.name, i,

					mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);

		}

	} else {

		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {

			I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],

					"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",

					crtc->base.base.id, crtc->base.name, i,

					mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);

		}

	}



	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {

drivers/gpu/drm/i915/display/intel_display_power.c

+2 −2
Original line number Diff line number Diff line
@@ -405,8 +405,8 @@ print_async_put_domains_state(struct i915_power_domains *power_domains) 
						     struct drm_i915_private,

						     display.power.domains);



	drm_dbg(&i915->drm, "async_put_wakeref %lu\n",

		power_domains->async_put_wakeref);

	drm_dbg(&i915->drm, "async_put_wakeref: %s\n",

		str_yes_no(power_domains->async_put_wakeref));



	print_power_domains(power_domains, "async_put_domains[0]",

			    &power_domains->async_put_domains[0]);

drivers/gpu/drm/i915/display/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -2101,7 +2101,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 
		}

	}



	dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);

	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);

	if (!dsc_max_bpc)

		return -EINVAL;

drivers/gpu/drm/i915/display/intel_psr.c

+5 −5
Original line number Diff line number Diff line
@@ -3319,11 +3319,11 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector) 
	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	struct dentry *root = connector->base.debugfs_entry;



	if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) {

		if (!(HAS_DP20(i915) &&

		      connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort))

	/* TODO: Add support for MST connectors as well. */

	if ((connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&

	     connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||

	    connector->mst_port)

		return;

	}



	debugfs_create_file("i915_psr_sink_status", 0444, root,

			    connector, &i915_psr_sink_status_fops);

drivers/gpu/drm/i915/gem/i915_gem_context_types.h

+2 −2
Original line number Diff line number Diff line
@@ -412,9 +412,9 @@ struct i915_gem_context { 


	/** @stale: tracks stale engines to be destroyed */

	struct {

		/** @lock: guards engines */

		/** @stale.lock: guards engines */

		spinlock_t lock;

		/** @engines: list of stale engines */

		/** @stale.engines: list of stale engines */

		struct list_head engines;

	} stale;

};