dt-bindings: clock: sophgo: add pll clocks for SG2042

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo SG2042 PLL Clock Generator

maintainers:

  - Chen Wang <unicorn_wang@outlook.com>

properties:

  compatible:

    const: sophgo,sg2042-pll

  reg:

    maxItems: 1

  clocks:

    items:

      - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)

      - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)

      - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)

  clock-names:

    items:

      - const: cgi_main

      - const: cgi_dpll0

      - const: cgi_dpll1

  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

additionalProperties: false

examples:

  - |

    clock-controller@10000000 {

      compatible = "sophgo,sg2042-pll";

      reg = <0x10000000 0x10000>;

      clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;

      clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";

      #clock-cells = <1>;

    };

/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */

/*

 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.

 */

#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__

#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__

#define MPLL_CLK			0

#define FPLL_CLK			1

#define DPLL0_CLK			2

#define DPLL1_CLK			3

#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */