Commit 88ad12c9 authored by Imre Deak's avatar Imre Deak Committed by Mika Kahola
Browse files

drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros 



Rename the PHY_C20_CUSTOM_SERDES / PHY_C20_CUSTOM_SERDES_MASK register
field names to PHY_C20_DP_RATE / PHY_C20_DP_RATE_MASK, and move the
definitions under the actual register containing the fields.

Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-2-mika.kahola@intel.com
parent f65223ba

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+3 −3
Original line number Diff line number Diff line
@@ -2700,12 +2700,12 @@ static void intel_c20_pll_program(struct intel_display *display, 
	/* 5. For DP or 6. For HDMI */

	if (is_dp) {

		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,

			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)),

			      BIT(6) | PHY_C20_DP_RATE_MASK,

			      BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),

			      MB_WRITE_COMMITTED);

	} else {

		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,

			      BIT(7) | PHY_C20_DP_RATE_MASK,

			      is_hdmi_frl(port_clock) ? BIT(7) : 0,

			      MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -298,10 +298,10 @@ 
#define PHY_C20_RD_DATA_L		0xC08

#define PHY_C20_RD_DATA_H		0xC09

#define PHY_C20_VDR_CUSTOM_SERDES_RATE	0xD00

#define   PHY_C20_DP_RATE_MASK		REG_GENMASK8(4, 1)

#define   PHY_C20_DP_RATE(val)		REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)

#define PHY_C20_VDR_HDMI_RATE		0xD01

#define   PHY_C20_CONTEXT_TOGGLE	REG_BIT8(0)

#define   PHY_C20_CUSTOM_SERDES_MASK	REG_GENMASK8(4, 1)

#define   PHY_C20_CUSTOM_SERDES(val)	REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)

#define PHY_C20_VDR_CUSTOM_WIDTH	0xD02

#define   PHY_C20_CUSTOM_WIDTH_MASK	REG_GENMASK(1, 0)

#define   PHY_C20_CUSTOM_WIDTH(val)	REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)