Commit 89103a16 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-04-05' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Weekly fixes, mostly xe and i915, amdgpu on a week off, otherwise a
  nouveau fix for a crash with new vulkan cts tests, and a couple of
  cleanups and misc fixes.

  display:
   - fix typos in kerneldoc

  prime:
   - unbreak dma-buf export for virt-gpu

  nouveau:
   - uvmm: fix remap address calculation
   - minor cleanups

  panfrost:
   - fix power-transition timeouts

  xe:
   - Stop using system_unbound_wq for preempt fences
   - Fix saving unordered rebinding fences by attaching them as kernel
     feces to the vm's resv
   - Fix TLB invalidation fences completing out of order
   - Move rebind TLB invalidation to the ring ops to reduce the latency

  i915:
   - A few DisplayPort related fixes
   - eDP PSR fixes
   - Remove some VM space restrictions on older platforms
   - Disable automatic load CCS load balancing"

* tag 'drm-fixes-2024-04-05' of https://gitlab.freedesktop.org/drm/kernel: (22 commits)
  drm/xe: Use ordered wq for preempt fence waiting
  drm/xe: Move vma rebinding to the drm_exec locking loop
  drm/xe: Make TLB invalidation fences unordered
  drm/xe: Rework rebinding
  drm/xe: Use ring ops TLB invalidation for rebinds
  drm/i915/mst: Reject FEC+MST on ICL
  drm/i915/mst: Limit MST+DSC to TGL+
  drm/i915/dp: Fix the computation for compressed_bpp for DISPLAY < 13
  drm/i915/gt: Enable only one CCS for compute workload
  drm/i915/gt: Do not generate the command streamer for all the CCS
  drm/i915/gt: Disable HW load balancing for CCS
  drm/i915/gt: Limit the reserved VM space to only the platforms that need it
  drm/i915/psr: Fix intel_psr2_sel_fetch_et_alignment usage
  drm/i915/psr: Move writing early transport pipe src
  drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT value
  drm/i915/dp: Remove support for UHBR13.5
  drm/i915/dp: Fix DSC state HW readout for SST connectors
  drm/display: fix typo
  drm/prime: Unbreak virtgpu dma-buf export
  nouveau/uvmm: fix addr/range calcs for remap operations
  ...
parents e8b0ccb2 4c859574

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
 * @adapter: I2C adapter for the DDC bus

 * @offset: register offset

 * @buffer: buffer for return data

 * @size: sizo of the buffer

 * @size: size of the buffer

 *

 * Reads @size bytes from the DP dual mode adaptor registers

 * starting at @offset.
@@ -116,7 +116,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_read); 
 * @adapter: I2C adapter for the DDC bus

 * @offset: register offset

 * @buffer: buffer for write data

 * @size: sizo of the buffer

 * @size: size of the buffer

 *

 * Writes @size bytes to the DP dual mode adaptor registers

 * starting at @offset.

drivers/gpu/drm/drm_prime.c

+6 −1
Original line number Diff line number Diff line
@@ -582,7 +582,12 @@ int drm_gem_map_attach(struct dma_buf *dma_buf, 
{

	struct drm_gem_object *obj = dma_buf->priv;



	if (!obj->funcs->get_sg_table)

	/*

	 * drm_gem_map_dma_buf() requires obj->get_sg_table(), but drivers

	 * that implement their own ->map_dma_buf() do not.

	 */

	if (dma_buf->ops->map_dma_buf == drm_gem_map_dma_buf &&

	    !obj->funcs->get_sg_table)

		return -ENOSYS;



	return drm_gem_pin(obj);

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ gt-y += \ 
	gt/intel_ggtt_fencing.o \

	gt/intel_gt.o \

	gt/intel_gt_buffer_pool.o \

	gt/intel_gt_ccs_mode.o \

	gt/intel_gt_clock_utils.o \

	gt/intel_gt_debugfs.o \

	gt/intel_gt_engines_debugfs.o \

drivers/gpu/drm/i915/display/intel_display.c

+0 −9
Original line number Diff line number Diff line
@@ -2709,15 +2709,6 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 
	 */

	intel_de_write(dev_priv, PIPESRC(pipe),

		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));



	if (!crtc_state->enable_psr2_su_region_et)

		return;



	width = drm_rect_width(&crtc_state->psr2_su_area);

	height = drm_rect_height(&crtc_state->psr2_su_area);



	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),

		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));

}



static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ struct drm_printer; 
#define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)

#define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)

#define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)

#define HAS_DSC_MST(__i915)		(DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915))

#define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)

#define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)

#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)