Commit 89629150 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
Browse files

drm/amdgpu: add vcn_v4_0_3 ip dump support 



Add support of vcn ip dump in the devcoredump
for vcn_v4_0_3.

Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f3c958ab

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

+80 −1
Original line number Diff line number Diff line
@@ -45,6 +45,42 @@ 
#define VCN_VID_SOC_ADDRESS_2_0		0x1fb00

#define VCN1_VID_SOC_ADDRESS_3_0	0x48300



static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),

	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)

};



#define NORMALIZE_VCN_REG_OFFSET(offset) \

		(offset & 0x1FFFF)
@@ -92,6 +128,8 @@ static int vcn_v4_0_3_sw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_ring *ring;

	int i, r, vcn_inst;

	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);

	uint32_t *ptr;



	r = amdgpu_vcn_sw_init(adev);

	if (r)
@@ -159,6 +197,15 @@ static int vcn_v4_0_3_sw_init(void *handle) 
		}

	}



	/* Allocate memory for VCN IP Dump buffer */

	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);

	if (!ptr) {

		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");

		adev->vcn.ip_dump = NULL;

	} else {

		adev->vcn.ip_dump = ptr;

	}



	return 0;

}
@@ -194,6 +241,8 @@ static int vcn_v4_0_3_sw_fini(void *handle) 


	r = amdgpu_vcn_sw_fini(adev);



	kfree(adev->vcn.ip_dump);



	return r;

}
@@ -1684,6 +1733,36 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 
	adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;

}



static void vcn_v4_0_3_dump_ip_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int i, j;

	bool is_powered;

	uint32_t inst_off, inst_id;

	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);



	if (!adev->vcn.ip_dump)

		return;



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		if (adev->vcn.harvest_config & (1 << i))

			continue;



		inst_id = GET_INST(VCN, i);

		inst_off = i * reg_count;

		/* mmUVD_POWER_STATUS is always readable and is first element of the array */

		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);

		is_powered = (adev->vcn.ip_dump[inst_off] &

				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;



		if (is_powered)

			for (j = 1; j < reg_count; j++)

				adev->vcn.ip_dump[inst_off + j] =

					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],

									   inst_id));

	}

}



static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {

	.name = "vcn_v4_0_3",

	.early_init = vcn_v4_0_3_early_init,
@@ -1702,7 +1781,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 
	.post_soft_reset = NULL,

	.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,

	.set_powergating_state = vcn_v4_0_3_set_powergating_state,

	.dump_ip_state = NULL,

	.dump_ip_state = vcn_v4_0_3_dump_ip_state,

	.print_ip_state = NULL,

};