Commit 89713ce5 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Enable Request rate limiter during C-State on dcn401 



[WHY]
When C-State entry is requested, the rate limiter will be disabled
which can result in high contention in the DCHUB return path.

[HOW]
Enable the rate limiter during C-state requests to prevent contention.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 27227a23

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

+6 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 








#define DML2_MAX_FMT_420_BUFFER_WIDTH 4096









#define DML_MAX_NUM_OF_SLICES_PER_DSC 4









#define ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE

















const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)









{








@@ -3886,6 +3887,10 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch







#endif

















	*p->hw_debug5 = false;









#ifdef ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE









	if (p->NumberOfActiveSurfaces > 1)









		*p->hw_debug5 = true;









#else









	for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {









		if (!(p->mrq_present) && (!(*p->UnboundedRequestEnabled)) && (TotalActiveDPP == 1)









			&& p->display_cfg->plane_descriptors[k].surface.dcc.enable








@@ -3901,6 +3906,7 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch







		dml2_printf("DML::%s: k=%u hw_debug5 = %u\n", __func__, k, *p->hw_debug5);









#endif









	}









#endif









}

















static enum dml2_odm_mode DecideODMMode(unsigned int HActive,
































drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h



+7
−1






























Original line number
Diff line number
Diff line







@@ -200,6 +200,7 @@ struct dcn_hubbub_registers {







	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B;









	uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1;









	uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2;









	uint32_t DCHUBBUB_CTRL_STATUS;









};



















#define HUBBUB_REG_FIELD_LIST_DCN32(type) \








@@ -320,7 +321,12 @@ struct dcn_hubbub_registers {







		type DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD;\









		type DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD;\









		type DCHUBBUB_TIMEOUT_DETECTION_EN;\









		type DCHUBBUB_TIMEOUT_TIMER_RESET









		type DCHUBBUB_TIMEOUT_TIMER_RESET;\









		type ROB_UNDERFLOW_STATUS;\









		type ROB_OVERFLOW_STATUS;\









		type ROB_OVERFLOW_CLEAR;\









		type DCHUBBUB_HW_DEBUG;\









		type CSTATE_SWATH_CHK_GOOD_MODE



















#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \









		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
































drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h



+1
−0






























Original line number
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Diff line







@@ -96,6 +96,7 @@ struct dcn20_hubbub {







	unsigned int det1_size;









	unsigned int det2_size;









	unsigned int det3_size;









	bool allow_sdpif_rate_limit_when_cstate_req;









};



















void hubbub2_construct(struct dcn20_hubbub *hubbub,
































drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c



+22
−2






























Original line number
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Diff line







@@ -1192,15 +1192,35 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst)







	}









}



















static void dcn401_program_timeout_thresholds(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs)









static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower)









{









	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);



















	bool wm_pending = false;









	uint32_t temp;



















	/* request backpressure and outstanding return threshold (unused)*/









	//REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold);



















	/* P-State stall threshold */









	REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold);



















	if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) {









		hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req;



















		/* only update the required bits */









		REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp);









		if (hubbub2->allow_sdpif_rate_limit_when_cstate_req) {









			temp |= (1 << 5);









		} else {









			temp &= ~(1 << 5);









		}









		REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp);









	} else {









		wm_pending = true;









	}



















	return wm_pending;









}



















static const struct hubbub_funcs hubbub4_01_funcs = {








@@ -1226,7 +1246,7 @@ static const struct hubbub_funcs hubbub4_01_funcs = {







	.program_det_segments = dcn401_program_det_segments,









	.program_compbuf_segments = dcn401_program_compbuf_segments,









	.wait_for_det_update = dcn401_wait_for_det_update,









	.program_timeout_thresholds = dcn401_program_timeout_thresholds,









	.program_arbiter = dcn401_program_arbiter,









};



















void hubbub401_construct(struct dcn20_hubbub *hubbub2,
































drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h



+6
−1






























Original line number
Diff line number
Diff line







@@ -128,7 +128,12 @@







	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\









	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\









	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\









	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh)









	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh),\









	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_UNDERFLOW_STATUS, mask_sh),\









	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_STATUS, mask_sh),\









	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_CLEAR, mask_sh),\









	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, mask_sh),\









	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, CSTATE_SWATH_CHK_GOOD_MODE, mask_sh)



















bool hubbub401_program_urgent_watermarks(









		struct hubbub *hubbub,