Commit 897adaf5 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

clk: rockchip: rk3036: fix implementation of usb480m clock mux 



Contrary to how it is implemented right now, this mux is controllable via
a bit in CRU_MUSC_CON (same bit as on rk3128 even) and allows switching
between xin24m and the 480m output of the usb2phy.

So drop the hard-coded fixed-factor clock and implement the correct mux
instead.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250503202532.992033-3-heiko@sntech.de
parent 6e06b641

drivers/clk/rockchip/clk-rk3036.c

+4 −6
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; 
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };

PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };



PNAME(mux_usb480m_p)	= { "usb480m_phy", "xin24m" };

PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };

PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };

PNAME(mux_i2s_clkout_p)	= { "i2s_pre", "xin12m" };
@@ -423,6 +424,9 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),

	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),

	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),



	MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,

			RK2928_MISC_CON, 15, 1, MFLAGS),

};



static const char *const rk3036_critical_clocks[] __initconst = {
@@ -438,7 +442,6 @@ static void __init rk3036_clk_init(struct device_node *np) 
	struct rockchip_clk_provider *ctx;

	unsigned long clk_nr_clks;

	void __iomem *reg_base;

	struct clk *clk;



	reg_base = of_iomap(np, 0);

	if (!reg_base) {
@@ -462,11 +465,6 @@ static void __init rk3036_clk_init(struct device_node *np) 
		return;

	}



	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_plls(ctx, rk3036_pll_clks,

				   ARRAY_SIZE(rk3036_pll_clks),

				   RK3036_GRF_SOC_STATUS0);