Commit 89830c62 authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: On boot disable domain22 force power on 



[Why]
HDCP2 enablement fails when domain22 is set to force
power on

[How]
Disable force power on for domain22 on startup

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9256e8d4

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c

+9 −1
Original line number Diff line number Diff line
@@ -332,6 +332,13 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) 
	pg_cntl->pg_res_enable[PG_DCIO] = power_on;

}



void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on)

{

	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);



	REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, power_on ? 1 : 0);

}



static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)

{

	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
@@ -501,7 +508,8 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = { 
	.mpcc_pg_control = pg_cntl35_mpcc_pg_control,

	.opp_pg_control = pg_cntl35_opp_pg_control,

	.optc_pg_control = pg_cntl35_optc_pg_control,

	.dwb_pg_control = pg_cntl35_dwb_pg_control

	.dwb_pg_control = pg_cntl35_dwb_pg_control,

	.set_force_poweron_domain22 = pg_cntl35_set_force_poweron_domain22

};



struct pg_cntl *pg_cntl35_create(

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h

+1 −0
Original line number Diff line number Diff line
@@ -183,6 +183,7 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl, 
	unsigned int optc_inst, bool power_on);

void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);

void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);

void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on);



struct pg_cntl *pg_cntl35_create(

	struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+3 −0
Original line number Diff line number Diff line
@@ -311,6 +311,9 @@ void dcn35_init_hw(struct dc *dc) 
	if (dc->res_pool->pg_cntl) {

		if (dc->res_pool->pg_cntl->funcs->init_pg_status)

			dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);



		if (dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22)

			dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22(dc->res_pool->pg_cntl, false);

	}

}

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ struct pg_cntl_funcs { 
	void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);

	void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);

	void (*init_pg_status)(struct pg_cntl *pg_cntl);



	void (*set_force_poweron_domain22)(struct pg_cntl *pg_cntl, bool power_on);

};



#endif //__DC_PG_CNTL_H__