Commit 8984f97c authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dmitry Baryshkov
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drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU 



v12.0 DPU on SM8750 comes with 10-bit color alpha.  Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().

Notable changes in v6:
Correct fg_alpha shift on new DPU, pointed out by Abel Vesas.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/659629/
Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-10-a591c609743d@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent afff6425

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+16 −7
Original line number Diff line number Diff line
@@ -320,14 +320,22 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, 
}



static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,

		struct dpu_plane_state *pstate, const struct msm_format *format)

				      struct dpu_plane_state *pstate,

				      const struct msm_format *format,

				      const struct dpu_mdss_version *mdss_ver)

{

	struct dpu_hw_mixer *lm = mixer->hw_lm;

	u32 blend_op;

	u32 fg_alpha, bg_alpha;

	u32 fg_alpha, bg_alpha, max_alpha;



	if (mdss_ver->core_major_ver < 12) {

		max_alpha = 0xff;

		fg_alpha = pstate->base.alpha >> 8;

	bg_alpha = 0xff - fg_alpha;

	} else {

		max_alpha = 0x3ff;

		fg_alpha = pstate->base.alpha >> 6;

	}

	bg_alpha = max_alpha - fg_alpha;



	/* default to opaque blending */

	if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
@@ -337,7 +345,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 
	} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {

		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |

			DPU_BLEND_BG_ALPHA_FG_PIXEL;

		if (fg_alpha != 0xff) {

		if (fg_alpha != max_alpha) {

			bg_alpha = fg_alpha;

			blend_op |= DPU_BLEND_BG_MOD_ALPHA |

				    DPU_BLEND_BG_INV_MOD_ALPHA;
@@ -348,7 +356,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 
		/* coverage blending */

		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |

			DPU_BLEND_BG_ALPHA_FG_PIXEL;

		if (fg_alpha != 0xff) {

		if (fg_alpha != max_alpha) {

			bg_alpha = fg_alpha;

			blend_op |= DPU_BLEND_FG_MOD_ALPHA |

				    DPU_BLEND_FG_INV_MOD_ALPHA |
@@ -481,7 +489,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 


		/* blend config update */

		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {

			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);

			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format,

						  ctl->mdss_ver);



			if (bg_alpha_enable && !format->alpha_enable)

				mixer[lm_idx].mixer_op_mode = 0;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

+81 −3
Original line number Diff line number Diff line
@@ -19,12 +19,20 @@ 


/* These register are offset to mixer base + stage base */

#define LM_BLEND0_OP                     0x00



/* <v12 DPU with offset to mixer base + stage base */

#define LM_BLEND0_CONST_ALPHA            0x04

#define LM_FG_COLOR_FILL_COLOR_0         0x08

#define LM_FG_COLOR_FILL_COLOR_1         0x0C

#define LM_FG_COLOR_FILL_SIZE            0x10

#define LM_FG_COLOR_FILL_XY              0x14



/* >= v12 DPU */

#define LM_BORDER_COLOR_0_V12            0x1c

#define LM_BORDER_COLOR_1_V12            0x20



/* >= v12 DPU with offset to mixer base + stage base */

#define LM_BLEND0_CONST_ALPHA_V12        0x08

#define LM_BLEND0_FG_ALPHA               0x04

#define LM_BLEND0_BG_ALPHA               0x08
@@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 
	}

}



static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,

					     struct dpu_mdss_color *color,

					     u8 border_en)

{

	struct dpu_hw_blk_reg_map *c = &ctx->hw;



	if (border_en) {

		DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,

			      (color->color_0 & 0x3ff) |

			      ((color->color_1 & 0x3ff) << 16));

		DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,

			      (color->color_2 & 0x3ff) |

			      ((color->color_3 & 0x3ff) << 16));

	}

}



static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)

{

	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
@@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx 
	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);

}



static void

dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,

						u32 stage, u32 fg_alpha,

						u32 bg_alpha, u32 blend_op)

{

	struct dpu_hw_blk_reg_map *c = &ctx->hw;

	int stage_off;

	u32 const_alpha;



	if (stage == DPU_STAGE_BASE)

		return;



	stage_off = _stage_offset(ctx, stage);

	if (WARN_ON(stage_off < 0))

		return;



	const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);

	DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);

	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);

}



static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,

	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)

{
@@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, 
	DPU_REG_WRITE(c, LM_OP_MODE, op_mode);

}



static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,

				       uint32_t mixer_op_mode)

{

	struct dpu_hw_blk_reg_map *c = &ctx->hw;

	int op_mode, stages, stage_off, i;



	stages = ctx->cap->sblk->maxblendstages;

	if (stages <= 0)

		return;



	for (i = DPU_STAGE_0; i <= stages; i++) {

		stage_off = _stage_offset(ctx, i);

		if (WARN_ON(stage_off < 0))

			return;



		/* set color_out3 bit in blend0_op when enabled in mixer_op_mode */

		op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);

		if (mixer_op_mode & BIT(i))

			op_mode |= BIT(30);

		else

			op_mode &= ~BIT(30);



		DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);

	}

}



/**

 * dpu_hw_lm_init() - Initializes the mixer hw driver object.

 * should be called once before accessing every mixer.
@@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 
	c->idx = cfg->id;

	c->cap = cfg;

	c->ops.setup_mixer_out = dpu_hw_lm_setup_out;

	if (mdss_ver->core_major_ver >= 4)

	if (mdss_ver->core_major_ver >= 12)

		c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;

	else if (mdss_ver->core_major_ver >= 4)

		c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;

	else

		c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;

	if (mdss_ver->core_major_ver < 12) {

		c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;

		c->ops.setup_border_color = dpu_hw_lm_setup_border_color;

	} else {

		c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;

		c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;

	}

	c->ops.setup_misr = dpu_hw_lm_setup_misr;

	c->ops.collect_misr = dpu_hw_lm_collect_misr;