Commit 89a410b2 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Wa_18028616096 now applies to all DG2 



The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231115182117.2551522-2-matthew.d.roper@intel.com
parent d3715a64

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −5
Original line number Diff line number Diff line
@@ -2937,6 +2937,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
		 * Wa_22015475538:dg2

		 */

		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);



		/* Wa_18028616096 */

		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);

	}



	if (IS_DG2_G11(i915)) {
@@ -2965,11 +2968,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
			   true);

	}



	if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {

		/* Wa_18028616096 */

		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);

	}



	if (IS_XEHPSDV(i915)) {

		/* Wa_1409954639 */

		wa_mcr_masked_en(wal,