Unverified Commit 89db0793 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Krzysztof Wilczyński
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PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling 



Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.

In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
field there is another one which needs to be updated.

It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
the very least the maximum link-width capability CSR won't expose the
actual maximum capability.

[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.60a, March 2015, p.1032
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.70a, March 2016, p.1065
[3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.90a, March 2016, p.1057
...
[X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
      Version 5.40a, March 2019, p.1396
[X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
      Version 5.40a, March 2019, p.1266

Suggested-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/linux-pci/20231018085631.1121289-4-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarSerge Semin <fancer.lancer@gmail.com>
parent a9a1bcba

drivers/pci/controller/dwc/pcie-designware.c

+8 −1
Original line number Diff line number Diff line
@@ -734,7 +734,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) 


static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)

{

	u32 lwsc, plc;

	u32 lnkcap, lwsc, plc;

	u8 cap;



	if (!num_lanes)

		return;
@@ -770,6 +771,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 
	}

	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);

	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);



	cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);

	lnkcap &= ~PCI_EXP_LNKCAP_MLW;

	lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);

	dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);

}



void dw_pcie_iatu_detect(struct dw_pcie *pci)