Unverified Commit 89f4fd7b authored by Eric Chan's avatar Eric Chan Committed by Palmer Dabbelt
Browse files

riscv/barrier: Define __{mb,rmb,wmb} 



Introduce __{mb,rmb,wmb}, and rely on the generic definitions for
{mb,rmb,wmb}. Although KCSAN is not supported yet, the definitions can
be made more consistent with generic instrumentation. Also add a space
to make the changes pass check by checkpatch.pl.
Without the space, the error message is as below:
ERROR: space required after that ',' (ctx:VxV)
26: FILE: arch/riscv/include/asm/barrier.h:23:
+#define __mb()         RISCV_FENCE(iorw,iorw)
                                        ^

Signed-off-by: default avatarEric Chan <ericchancf@google.com>
Reviewed-by: default avatarAndrea Parri <parri.andrea@gmail.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Tested-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240217131249.3668103-1-ericchancf@google.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 6613476e

arch/riscv/include/asm/barrier.h

+3 −3
Original line number Diff line number Diff line
@@ -20,9 +20,9 @@ 
	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")



/* These barriers need to enforce ordering on both devices or memory. */

#define mb()		RISCV_FENCE(iorw,iorw)

#define rmb()		RISCV_FENCE(ir,ir)

#define wmb()		RISCV_FENCE(ow,ow)

#define __mb()		RISCV_FENCE(iorw, iorw)

#define __rmb()		RISCV_FENCE(ir, ir)

#define __wmb()		RISCV_FENCE(ow, ow)



/* These barriers do not need to enforce ordering on devices, just memory. */

#define __smp_mb()	RISCV_FENCE(rw,rw)