Unverified Commit 8a30a6d3 authored by Bogdan-Gabriel Roman's avatar Bogdan-Gabriel Roman Committed by Mark Brown
Browse files

spi: spi-fsl-dspi: Halt the module after a new message transfer 



The XSPI mode implementation in this driver still uses the EOQ flag to
signal the last word in a transmission and deassert the PCS signal.
However, at speeds lower than ~200kHZ, the PCS signal seems to remain
asserted even when SR[EOQF] = 1 indicates the end of a transmission.
This is a problem for target devices which require the deassertation of
the PCS signal between transfers.

Hence, this commit 'forces' the deassertation of the PCS by stopping the
module through MCR[HALT] after completing a new transfer. According to
the reference manual, the module stops or transitions from the Running
state to the Stopped state after the current frame, when any one of the
following conditions exist:
- The value of SR[EOQF] = 1.
- The chip is in Debug mode and the value of MCR[FRZ] = 1.
- The value of MCR[HALT] = 1.

This shouldn't be done if the last transfer in the message has cs_change
set.

Fixes: ea93ed4c ("spi: spi-fsl-dspi: Use EOQ for last word in buffer even for XSPI mode")
Signed-off-by: default avatarBogdan-Gabriel Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: default avatarLarisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-2-bea884630cfb@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 283ae0c6

drivers/spi/spi-fsl-dspi.c

+24 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
#define SPI_SR_TFIWF			BIT(18)

#define SPI_SR_RFDF			BIT(17)

#define SPI_SR_CMDFFF			BIT(16)

#define SPI_SR_TXRXS			BIT(30)

#define SPI_SR_CLEAR			(SPI_SR_TCFQF | \

					SPI_SR_TFUF | SPI_SR_TFFF | \

					SPI_SR_CMDTCF | SPI_SR_SPEF | \
@@ -921,9 +922,20 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
	struct spi_transfer *transfer;

	bool cs = false;

	int status = 0;

	u32 val = 0;

	bool cs_change = false;



	message->actual_length = 0;



	/* Put DSPI in running mode if halted. */

	regmap_read(dspi->regmap, SPI_MCR, &val);

	if (val & SPI_MCR_HALT) {

		regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, 0);

		while (regmap_read(dspi->regmap, SPI_SR, &val) >= 0 &&

		       !(val & SPI_SR_TXRXS))

			;

	}



	list_for_each_entry(transfer, &message->transfers, transfer_list) {

		dspi->cur_transfer = transfer;

		dspi->cur_msg = message;
@@ -953,6 +965,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
				dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;

		}



		cs_change = transfer->cs_change;

		dspi->tx = transfer->tx_buf;

		dspi->rx = transfer->rx_buf;

		dspi->len = transfer->len;
@@ -988,6 +1001,15 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
			dspi_deassert_cs(spi, &cs);

	}



	if (status || !cs_change) {

		/* Put DSPI in stop mode */

		regmap_update_bits(dspi->regmap, SPI_MCR,

				   SPI_MCR_HALT, SPI_MCR_HALT);

		while (regmap_read(dspi->regmap, SPI_SR, &val) >= 0 &&

		       val & SPI_SR_TXRXS)

			;

	}



	message->status = status;

	spi_finalize_current_message(ctlr);
@@ -1245,6 +1267,8 @@ static int dspi_init(struct fsl_dspi *dspi) 
	if (!spi_controller_is_target(dspi->ctlr))

		mcr |= SPI_MCR_HOST;



	mcr |= SPI_MCR_HALT;



	regmap_write(dspi->regmap, SPI_MCR, mcr);

	regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);