Commit 8a5a0294 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,r9a09g077/87: Add USB_CLK clock ID 



Add the USB clock (USB_CLK) definition for the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs.  USB_CLK is used as the
reference clock for USB PHY layer.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250804202643.3967484-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 8f5ae30d

include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

+1 −0
Original line number Diff line number Diff line
@@ -25,5 +25,6 @@ 
#define R9A09G077_CLK_PCLKM		13

#define R9A09G077_CLK_PCLKL		14

#define R9A09G077_SDHI_CLKHS		15

#define R9A09G077_USB_CLK		16



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

+1 −0
Original line number Diff line number Diff line
@@ -25,5 +25,6 @@ 
#define R9A09G087_CLK_PCLKM		13

#define R9A09G087_CLK_PCLKL		14

#define R9A09G087_SDHI_CLKHS		15

#define R9A09G087_USB_CLK		16



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */