Commit 8a5c3ef7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soundwire-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire 

Pull soundwire fix from Vinod Koul:

 - Single AMD driver fix for wake interrupt handling in clockstop mode

* tag 'soundwire-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire:
  soundwire: amd: fix for wake interrupt handling for clockstop mode
parents 6fba14a7 63dc588e

drivers/soundwire/amd_manager.c

+15 −0
Original line number Diff line number Diff line
@@ -130,6 +130,19 @@ static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 
	writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);

}



static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)

{

	u32 wake_ctrl;



	wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);

	if (enable)

		wake_ctrl |= AMD_SDW_WAKE_INTR_MASK;

	else

		wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK;



	writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);

}



static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,

				  int cmd_offset)

{
@@ -1095,6 +1108,7 @@ static int __maybe_unused amd_suspend(struct device *dev) 
	}



	if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {

		amd_sdw_wake_enable(amd_manager, false);

		return amd_sdw_clock_stop(amd_manager);

	} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {

		/*
@@ -1121,6 +1135,7 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev) 
		return 0;

	}

	if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {

		amd_sdw_wake_enable(amd_manager, true);

		return amd_sdw_clock_stop(amd_manager);

	} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {

		ret = amd_sdw_clock_stop(amd_manager);

drivers/soundwire/amd_manager.h

+2 −1
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ 
#define AMD_SDW0_EXT_INTR_MASK		0x200000

#define AMD_SDW1_EXT_INTR_MASK		4

#define AMD_SDW_IRQ_MASK_0TO7		0x77777777

#define AMD_SDW_IRQ_MASK_8TO11		0x000d7777

#define AMD_SDW_IRQ_MASK_8TO11		0x000c7777

#define AMD_SDW_IRQ_ERROR_MASK		0xff

#define AMD_SDW_MAX_FREQ_NUM		1

#define AMD_SDW0_MAX_TX_PORTS		3
@@ -190,6 +190,7 @@ 
#define AMD_SDW_CLK_RESUME_REQ				2

#define AMD_SDW_CLK_RESUME_DONE				3

#define AMD_SDW_WAKE_STAT_MASK				BIT(16)

#define AMD_SDW_WAKE_INTR_MASK				BIT(16)



static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {

	AMD_SDW_DEFAULT_CLK_FREQ,