Commit 8a6286c1 authored by Jiri Pirko's avatar Jiri Pirko Committed by Jakub Kicinski
Browse files

dpll: expose fractional frequency offset value to user 



Add a new netlink attribute to expose fractional frequency offset value
for a pin. Add an op to get the value from the driver.

Signed-off-by: default avatarJiri Pirko <jiri@nvidia.com>
Acked-by: default avatarVadim Fedorenko <vadim.fedorenko@linux.dev>
Acked-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Link: https://lore.kernel.org/r/20240103132838.1501801-2-jiri@resnulli.us


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 82e7b22f

Documentation/netlink/specs/dpll.yaml

+11 −0
Original line number Diff line number Diff line
@@ -296,6 +296,16 @@ attribute-sets: 
      -

        name: phase-offset

        type: s64

      -

        name: fractional-frequency-offset

        type: sint

        doc: |

          The FFO (Fractional Frequency Offset) between the RX and TX

          symbol rate on the media associated with the pin:

          (rx_frequency-tx_frequency)/rx_frequency

          Value is in PPM (parts per million).

          This may be implemented for example for pin of type

          PIN_TYPE_SYNCE_ETH_PORT.

  -

    name: pin-parent-device

    subset-of: pin
@@ -460,6 +470,7 @@ operations: 
            - phase-adjust-min

            - phase-adjust-max

            - phase-adjust

            - fractional-frequency-offset



      dump:

        pre: dpll-lock-dumpit

drivers/dpll/dpll_netlink.c

+24 −0
Original line number Diff line number Diff line
@@ -263,6 +263,27 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 
	return 0;

}



static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin,

			    struct dpll_pin_ref *ref,

			    struct netlink_ext_ack *extack)

{

	const struct dpll_pin_ops *ops = dpll_pin_ops(ref);

	struct dpll_device *dpll = ref->dpll;

	s64 ffo;

	int ret;



	if (!ops->ffo_get)

		return 0;

	ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

			   dpll, dpll_priv(dpll), &ffo, extack);

	if (ret) {

		if (ret == -ENODATA)

			return 0;

		return ret;

	}

	return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, ffo);

}



static int

dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,

		      struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
@@ -440,6 +461,9 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 
			prop->phase_range.max))

		return -EMSGSIZE;

	ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);

	if (ret)

		return ret;

	ret = dpll_msg_add_ffo(msg, pin, ref, extack);

	if (ret)

		return ret;

	if (xa_empty(&pin->parent_refs))

include/linux/dpll.h

+3 −0
Original line number Diff line number Diff line
@@ -77,6 +77,9 @@ struct dpll_pin_ops { 
				const struct dpll_device *dpll, void *dpll_priv,

				const s32 phase_adjust,

				struct netlink_ext_ack *extack);

	int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,

		       const struct dpll_device *dpll, void *dpll_priv,

		       s64 *ffo, struct netlink_ext_ack *extack);

};



struct dpll_pin_frequency {

include/uapi/linux/dpll.h

+1 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ enum dpll_a_pin { 
	DPLL_A_PIN_PHASE_ADJUST_MAX,

	DPLL_A_PIN_PHASE_ADJUST,

	DPLL_A_PIN_PHASE_OFFSET,

	DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,



	__DPLL_A_PIN_MAX,

	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)