Commit 8ae27234 authored by Alan Previn's avatar Alan Previn Committed by John Harrison
Browse files

drm/i915/pxp/mtl: Update pxp-firmware response timeout 



Update the max GSC-fw response time to match updated internal
fw specs. Because this response time is an SLA on the firmware,
not inclusive of i915->GuC->HW handoff latency, when submitting
requests to the GSC fw via intel_gsc_uc_heci_cmd_submit helpers,
start the count after the request hits the GSC command streamer.
Also, move GSC_REPLY_LATENCY_MS definition from pxp header to
intel_gsc_uc_heci_cmd_submit.h since its for any GSC HECI packet.

Signed-off-by: default avatarAlan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: default avatarVivaik Balasubrawmanian <vivaik.balasubrawmanian@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230917211933.1407559-2-alan.previn.teres.alexis@intel.com
parent 4d938bb9

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

+18 −2
Original line number Diff line number Diff line
@@ -81,8 +81,17 @@ int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64 addr_in, 


	i915_request_add(rq);



	if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)

	if (!err) {

		/*

		 * Start timeout for i915_request_wait only after considering one possible

		 * pending GSC-HECI submission cycle on the other (non-privileged) path.

		 */

		if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))

			drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,

				"Delay in gsc-heci-priv submission to gsccs-hw");

		if (i915_request_wait(rq, 0, msecs_to_jiffies(GSC_HECI_REPLY_LATENCY_MS)) < 0)

			err = -ETIME;

	}



	i915_request_put(rq);
@@ -186,6 +195,13 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, 
	i915_request_add(rq);



	if (!err) {

		/*

		 * Start timeout for i915_request_wait only after considering one possible

		 * pending GSC-HECI submission cycle on the other (privileged) path.

		 */

		if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))

			drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,

				"Delay in gsc-heci-non-priv submission to gsccs-hw");

		if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,

				      msecs_to_jiffies(timeout_ms)) < 0)

			err = -ETIME;

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

+6 −0
Original line number Diff line number Diff line
@@ -12,6 +12,12 @@ struct i915_vma; 
struct intel_context;

struct intel_gsc_uc;



#define GSC_HECI_REPLY_LATENCY_MS 500

/*

 * Max FW response time is 500ms, but this should be counted from the time the

 * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB.

 */



struct intel_gsc_mtl_header {

	u32 validity_marker;

#define GSC_HECI_VALIDITY_MARKER 0xA578875A

drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c

+1 −1
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ gsccs_send_message(struct intel_pxp *pxp, 


	ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&gt->uc.gsc,

						   exec_res->ce, &pkt, exec_res->bb_vaddr,

						   GSC_REPLY_LATENCY_MS);

						   GSC_HECI_REPLY_LATENCY_MS);

	if (ret) {

		drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);

		goto unlock;

drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h

+4 −6
Original line number Diff line number Diff line
@@ -8,16 +8,14 @@ 


#include <linux/types.h>



#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"



struct intel_pxp;



#define GSC_REPLY_LATENCY_MS 210

/*

 * Max FW response time is 200ms, to which we add 10ms to account for overhead

 * such as request preparation, GuC submission to hw and pipeline completion times.

 */

#define GSC_PENDING_RETRY_MAXCOUNT 40

#define GSC_PENDING_RETRY_PAUSE_MS 50

#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)

#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_HECI_REPLY_LATENCY_MS + \

					 (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS))



#ifdef CONFIG_DRM_I915_PXP

void intel_pxp_gsccs_fini(struct intel_pxp *pxp);