Commit 8afe6f0e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-12-22' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Pretty quiet for this week, just i915 and amdgpu fixes,

  I think the misc tree got lost this week, but didn't seem to have too
  much in it, so it can wait. I've also got a bunch of nouveau GSP fixes
  sailing around that'll probably land next time as well.

  amdgpu:
   - DCN 3.5 fixes
   - DCN 3.2 SubVP fix
   - GPUVM fix

  amdkfd:
   - SVM fix for APUs

  i915:
   - Fix state readout and check for DSC and bigjoiner combo
   - Fix a potential integer overflow
   - Reject async flips with bigjoiner
   - Fix MTL HDMI/DP PLL clock selection
   - Fix various issues by disabling pipe DMC events"

* tag 'drm-fixes-2023-12-22' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu: re-create idle bo's PTE during VM state machine reset
  drm/amd/display: dereference variable before checking for zero
  drm/amd/display: get dprefclk ss info from integration info table
  drm/amd/display: Add case for dcn35 to support usb4 dmub hpd event
  drm/amd/display: disable FPO and SubVP for older DMUB versions on DCN32x
  drm/amdkfd: svm range always mapped flag not working on APU
  drm/amd/display: Revert " drm/amd/display: Use channel_width = 2 for vram table 3.0"
  drm/i915/dmc: Don't enable any pipe DMC events
  drm/i915/mtl: Fix HDMI/DP PLL clock selection
  drm/i915: Reject async flips with bigjoiner
  drm/i915/hwmon: Fix static analysis tool reported issues
  drm/i915/display: Get bigjoiner config before dsc config during readout
parents 93a165cb d4b6e7f5
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+1 −0
Original line number Diff line number Diff line
@@ -285,6 +285,7 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
	list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
		struct amdgpu_bo *bo = vm_bo->bo;

		vm_bo->moved = true;
		if (!bo || bo->tbo.type != ttm_bo_type_kernel)
			list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
		else if (bo->parent)
+12 −6
Original line number Diff line number Diff line
@@ -1653,19 +1653,25 @@ static int svm_range_validate_and_map(struct mm_struct *mm,
			if (test_bit(gpuidx, prange->bitmap_access))
				bitmap_set(ctx->bitmap, gpuidx, 1);
		}

		/*
		 * If prange is already mapped or with always mapped flag,
		 * update mapping on GPUs with ACCESS attribute
		 */
		if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
			if (prange->mapped_to_gpu ||
			    prange->flags & KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED)
				bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);
		}
	} else {
		bitmap_or(ctx->bitmap, prange->bitmap_access,
			  prange->bitmap_aip, MAX_GPU_INSTANCE);
	}

	if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
		bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);
		if (!prange->mapped_to_gpu ||
		    bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
		r = 0;
		goto free_ctx;
	}
	}

	if (prange->actual_loc && !prange->ttm_res) {
		/* This should never happen. actual_loc gets set by
+15 −12
Original line number Diff line number Diff line
@@ -1014,13 +1014,20 @@ static enum bp_result get_ss_info_v4_5(
		DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
		break;
	case AS_SIGNAL_TYPE_DISPLAY_PORT:
		if (bp->base.integrated_info) {
			DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
			ss_info->spread_spectrum_percentage =
					bp->base.integrated_info->gpuclk_ss_percentage;
			ss_info->type.CENTER_MODE =
					bp->base.integrated_info->gpuclk_ss_type;
		} else {
			ss_info->spread_spectrum_percentage =
				disp_cntl_tbl->dp_ss_percentage;
			ss_info->spread_spectrum_range =
				disp_cntl_tbl->dp_ss_rate_10hz * 10;
			if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
				ss_info->type.CENTER_MODE = true;

		}
		DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
		break;
	case AS_SIGNAL_TYPE_GPU_PLL:
@@ -2386,13 +2393,7 @@ static enum bp_result get_vram_info_v30(
		return BP_RESULT_BADBIOSTABLE;

	info->num_chans = info_v30->channel_num;
	/* As suggested by VBIOS we should always use
	 * dram_channel_width_bytes = 2 when using VRAM
	 * table version 3.0. This is because the channel_width
	 * param in the VRAM info table is changed in 7000 series and
	 * no longer represents the memory channel width.
	 */
	info->dram_channel_width_bytes = 2;
	info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;

	return result;
}
@@ -2820,6 +2821,8 @@ static enum bp_result get_integrated_info_v2_2(
	info->ma_channel_number = info_v2_2->umachannelnumber;
	info->dp_ss_control =
		le16_to_cpu(info_v2_2->reserved1);
	info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
	info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;

	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
		info->ext_disp_conn_info.gu_id[i] =
+18 −8
Original line number Diff line number Diff line
@@ -5095,18 +5095,28 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
 */
bool dc_is_dmub_outbox_supported(struct dc *dc)
{
	switch (dc->ctx->asic_id.chip_family) {

	case FAMILY_YELLOW_CARP:
		/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
	if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
	    dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
		if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
		    !dc->debug.dpia_debug.bits.disable_dpia)
			return true;
	break;

	if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
	    !dc->debug.dpia_debug.bits.disable_dpia)
	case AMDGPU_FAMILY_GC_11_0_1:
	case AMDGPU_FAMILY_GC_11_5_0:
		if (!dc->debug.dpia_debug.bits.disable_dpia)
			return true;
	break;

	default:
		break;
	}

	/* dmub aux needs dmub notifications to be enabled */
	return dc->debug.enable_dmub_aux_for_legacy_ddc;

}

/**
+1 −1
Original line number Diff line number Diff line
@@ -5420,7 +5420,7 @@ static void CalculateOutputLink(
					*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,
												OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
					if (OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
					if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
						*RequiresDSC = true;
						LinkDSCEnable = true;
						*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,
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