Commit 8ba9fbe1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regularly scheduled fixes. The ttm one solves a problem of GPU drivers
  failing to load if debugfs is off in Kconfig, otherwise the i915 and
  mediatek, and amdgpu fixes all fairly normal.

  Nouveau has a couple of display fixes, but it has a fix for a
  longstanding race condition in it's memory manager code, and the fix
  mostly removes some code that wasn't working properly and has no
  userspace users. This fix makes the diffstat kinda larger but in a
  good (negative line-count) way.

  core:
   - fix drm_wait_vblank uapi copying bug

  ttm:
   - fix debugfs init when debugfs is off

  amdgpu:
   - vega10 SMU workload fix
   - DCN VM fix
   - DCN 3.01 watermark fix

  amdkfd:
   - SVM fix

  nouveau:
   - ampere display fixes
   - remove MM misfeature to fix a longstanding race condition

  i915:
   - tweaked display workaround for all PCHs
   - eDP MSO pipe sanity for ADL-P fix
   - remove unused symbol export

  mediatek:
   - AAL output size setting
   - Delete component in remove function"

* tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm:
  drm/amd/display: Use DCN30 watermark calc for DCN301
  drm/i915/dp: remove superfluous EXPORT_SYMBOL()
  drm/i915/edp: fix eDP MSO pipe sanity checks for ADL-P
  drm/i915: Tweaked Wa_14010685332 for all PCHs
  drm/nouveau: rip out nvkm_client.super
  drm/nouveau: block a bunch of classes from userspace
  drm/nouveau/fifo/nv50-: rip out dma channels
  drm/nouveau/kms/nv50: workaround EFI GOP window channel format differences
  drm/nouveau/disp: power down unused DP links during init
  drm/nouveau: recognise GA107
  drm: Copy drm_wait_vblank to user before returning
  drm/amd/display: Ensure DCN save after VM setup
  drm/amdkfd: fix random KFDSVMRangeTest.SetGetAttributesTest test failure
  drm/amd/pm: change the workload type for some cards
  Revert "drm/amd/pm: fix workload mismatch on vega10"
  drm: ttm: Don't bail from ttm_global_init if debugfs_create_dir fails
  drm/mediatek: Add component_del in OVL and COLOR remove function
  drm/mediatek: Add AAL output size configuration
parents 3db903a8 daa7772d

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

+8 −0
Original line number Diff line number Diff line
@@ -3026,6 +3026,14 @@ svm_range_get_attr(struct kfd_process *p, uint64_t start, uint64_t size, 
	pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start,

		 start + size - 1, nattr);



	/* Flush pending deferred work to avoid racing with deferred actions from

	 * previous memory map changes (e.g. munmap). Concurrent memory map changes

	 * can still race with get_attr because we don't hold the mmap lock. But that

	 * would be a race condition in the application anyway, and undefined

	 * behaviour is acceptable in that case.

	 */

	flush_work(&p->svms.deferred_list_work);



	mmap_read_lock(mm);

	if (!svm_range_is_valid(mm, start, size)) {

		pr_debug("invalid range\n");

drivers/gpu/drm/amd/display/dc/core/dc.c

+6 −0
Original line number Diff line number Diff line
@@ -1530,6 +1530,12 @@ void dc_z10_restore(struct dc *dc) 
	if (dc->hwss.z10_restore)

		dc->hwss.z10_restore(dc);

}



void dc_z10_save_init(struct dc *dc)

{

	if (dc->hwss.z10_save_init)

		dc->hwss.z10_save_init(dc);

}

#endif

/*

 * Applies given context to HW and copy it into current context.

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

+3 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c 
		 */

		memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));

		dc->vm_pa_config.valid = true;

#if defined(CONFIG_DRM_AMD_DC_DCN)

		dc_z10_save_init(dc);

#endif

	}



	return num_vmids;

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1338,6 +1338,7 @@ void dc_hardware_release(struct dc *dc); 
bool dc_set_psr_allow_active(struct dc *dc, bool enable);

#if defined(CONFIG_DRM_AMD_DC_DCN)

void dc_z10_restore(struct dc *dc);

void dc_z10_save_init(struct dc *dc);

#endif



bool dc_enable_dmub_notifications(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

+1 −95
Original line number Diff line number Diff line
@@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b 
	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

}



static void calculate_wm_set_for_vlevel(

		int vlevel,

		struct wm_range_table_entry *table_entry,

		struct dcn_watermarks *wm_set,

		struct display_mode_lib *dml,

		display_e2e_pipe_params_st *pipes,

		int pipe_cnt)

{

	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;



	ASSERT(vlevel < dml->soc.num_states);

	/* only pipe 0 is read for voltage and dcf/soc clocks */

	pipes[0].clks_cfg.voltage = vlevel;

	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;

	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;



	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;

	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;

	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;



	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;

	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;

	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;

	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;

	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;

	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;

	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;

	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;

	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;



}



static void dcn301_calculate_wm_and_dlg(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int pipe_cnt,

		int vlevel_req)

{

	int i, pipe_idx;

	int vlevel, vlevel_max;

	struct wm_range_table_entry *table_entry;

	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;



	ASSERT(bw_params);



	vlevel_max = bw_params->clk_table.num_entries - 1;



	/* WM Set D */

	table_entry = &bw_params->wm_table.entries[WM_D];

	if (table_entry->wm_type == WM_TYPE_RETRAINING)

		vlevel = 0;

	else

		vlevel = vlevel_max;

	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,

						&context->bw_ctx.dml, pipes, pipe_cnt);

	/* WM Set C */

	table_entry = &bw_params->wm_table.entries[WM_C];

	vlevel = min(max(vlevel_req, 2), vlevel_max);

	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,

						&context->bw_ctx.dml, pipes, pipe_cnt);

	/* WM Set B */

	table_entry = &bw_params->wm_table.entries[WM_B];

	vlevel = min(max(vlevel_req, 1), vlevel_max);

	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,

						&context->bw_ctx.dml, pipes, pipe_cnt);



	/* WM Set A */

	table_entry = &bw_params->wm_table.entries[WM_A];

	vlevel = min(vlevel_req, vlevel_max);

	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,

						&context->bw_ctx.dml, pipes, pipe_cnt);



	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;



		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);



		if (dc->config.forced_clocks) {

			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

		}

		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;



		pipe_idx++;

	}



	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

}



static struct resource_funcs dcn301_res_pool_funcs = {

	.destroy = dcn301_destroy_resource_pool,

	.link_enc_create = dcn301_link_encoder_create,

	.panel_cntl_create = dcn301_panel_cntl_create,

	.validate_bandwidth = dcn30_validate_bandwidth,

	.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,

	.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,

	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,

	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,

	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,