Commit 8bc7b360 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: split mmhub callbacks into ras and non-ras ones 



mmhub ras is only avaiable in cerntain mmhub ip
generation.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarJohn Clements <John.Clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 68d705dd

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+6 −5
Original line number Diff line number Diff line
@@ -3142,8 +3142,9 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) 
		if (adev->asic_reset_res)

			goto fail;



		if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)

			adev->mmhub.funcs->reset_ras_error_count(adev);

		if (adev->mmhub.ras_funcs &&

		    adev->mmhub.ras_funcs->reset_ras_error_count)

			adev->mmhub.ras_funcs->reset_ras_error_count(adev);

	} else {



		task_barrier_full(&hive->tb);
@@ -4378,9 +4379,9 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, 


	if (!r && amdgpu_ras_intr_triggered()) {

		list_for_each_entry(tmp_adev, device_list_handle, reset_list) {

			if (tmp_adev->mmhub.funcs &&

			    tmp_adev->mmhub.funcs->reset_ras_error_count)

				tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);

			if (tmp_adev->mmhub.ras_funcs &&

			    tmp_adev->mmhub.ras_funcs->reset_ras_error_count)

				tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev);

		}



		amdgpu_ras_intr_cleared();

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+25 −3
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
#include "amdgpu_gmc.h"

#include "amdgpu_ras.h"

#include "amdgpu_xgmi.h"

#include "mmhub_v1_0.h"

#include "mmhub_v9_4.h"

#include "mmhub_v1_7.h"



/**

 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
@@ -398,8 +401,25 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 
			return r;

	}



	if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) {

		r = adev->mmhub.funcs->ras_late_init(adev);

	/* initialize mmhub ras funcs */

	switch (adev->asic_type) {

	case CHIP_VEGA20:

		adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;

		break;

	case CHIP_ARCTURUS:

		adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;

		break;

	case CHIP_ALDEBARAN:

		adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;

		break;

	default:

		/* mmhub ras is not available */

		break;

	}



	if (adev->mmhub.ras_funcs &&

	    adev->mmhub.ras_funcs->ras_late_init) {

		r = adev->mmhub.ras_funcs->ras_late_init(adev);

		if (r)

			return r;

	}
@@ -423,6 +443,8 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 
	    adev->umc.ras_funcs->ras_fini)

		adev->umc.ras_funcs->ras_fini(adev);



	if (adev->mmhub.ras_funcs &&

	    adev->mmhub.ras_funcs->ras_fini)

		amdgpu_mmhub_ras_fini(adev);



	if (adev->gmc.xgmi.ras_funcs &&

drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h

+8 −4
Original line number Diff line number Diff line
@@ -21,12 +21,16 @@ 
#ifndef __AMDGPU_MMHUB_H__

#define __AMDGPU_MMHUB_H__



struct amdgpu_mmhub_funcs {

	void (*ras_init)(struct amdgpu_device *adev);

struct amdgpu_mmhub_ras_funcs {

	int (*ras_late_init)(struct amdgpu_device *adev);

	void (*ras_fini)(struct amdgpu_device *adev);

	void (*query_ras_error_count)(struct amdgpu_device *adev,

				      void *ras_error_status);

	void (*query_ras_error_status)(struct amdgpu_device *adev);

	void (*reset_ras_error_count)(struct amdgpu_device *adev);

};



struct amdgpu_mmhub_funcs {

	u64 (*get_fb_location)(struct amdgpu_device *adev);

	void (*init)(struct amdgpu_device *adev);

	int (*gart_enable)(struct amdgpu_device *adev);
@@ -40,12 +44,12 @@ struct amdgpu_mmhub_funcs { 
				uint64_t page_table_base);

	void (*update_power_gating)(struct amdgpu_device *adev,

                                bool enable);

	void (*query_ras_error_status)(struct amdgpu_device *adev);

};



struct amdgpu_mmhub {

	struct ras_common_if *ras_if;

	const struct amdgpu_mmhub_funcs *funcs;

	const struct amdgpu_mmhub_ras_funcs *ras_funcs;

};



int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+12 −8
Original line number Diff line number Diff line
@@ -799,11 +799,13 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 
			adev->gfx.funcs->query_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__MMHUB:

		if (adev->mmhub.funcs->query_ras_error_count)

			adev->mmhub.funcs->query_ras_error_count(adev, &err_data);

		if (adev->mmhub.ras_funcs &&

		    adev->mmhub.ras_funcs->query_ras_error_count)

			adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);



		if (adev->mmhub.funcs->query_ras_error_status)

			adev->mmhub.funcs->query_ras_error_status(adev);

		if (adev->mmhub.ras_funcs &&

		    adev->mmhub.ras_funcs->query_ras_error_status)

			adev->mmhub.ras_funcs->query_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__PCIE_BIF:

		if (adev->nbio.ras_funcs &&
@@ -857,8 +859,9 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 
			adev->gfx.funcs->reset_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__MMHUB:

		if (adev->mmhub.funcs->reset_ras_error_count)

			adev->mmhub.funcs->reset_ras_error_count(adev);

		if (adev->mmhub.ras_funcs &&

		    adev->mmhub.ras_funcs->reset_ras_error_count)

			adev->mmhub.ras_funcs->reset_ras_error_count(adev);

		break;

	case AMDGPU_RAS_BLOCK__SDMA:

		if (adev->sdma.funcs->reset_ras_error_count)
@@ -1515,8 +1518,9 @@ static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, 
			adev->gfx.funcs->query_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__MMHUB:

		if (adev->mmhub.funcs->query_ras_error_status)

			adev->mmhub.funcs->query_ras_error_status(adev);

		if (adev->mmhub.ras_funcs &&

		    adev->mmhub.ras_funcs->query_ras_error_status)

			adev->mmhub.ras_funcs->query_ras_error_status(adev);

		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+3 −2
Original line number Diff line number Diff line
@@ -1241,8 +1241,9 @@ static int gmc_v9_0_late_init(void *handle) 
		}

	}



	if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)

		adev->mmhub.funcs->reset_ras_error_count(adev);

	if (adev->mmhub.ras_funcs &&

	    adev->mmhub.ras_funcs->reset_ras_error_count)

		adev->mmhub.ras_funcs->reset_ras_error_count(adev);



	r = amdgpu_gmc_ras_late_init(adev);

	if (r)