Commit 8bfbe174 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Rodrigo Vivi
Browse files

drm/xe/xe2: Add workaround 14019449301 



This workaround applies to Xe2_LPM

V3(MattR):
  - Reorder reg and wa placement
  - Add base parameter to reg macro for better definition
V2(MattR):
  - Change name of register
  - Loop for all engines
  - Driver permanent WA, applies to all steps

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent f25d8291

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -112,6 +112,9 @@ 
#define RING_EXECLIST_CONTROL(base)		XE_REG((base) + 0x550)

#define	  EL_CTRL_LOAD				REG_BIT(0)



#define VDBOX_CGCTL3F08(base)                  XE_REG((base) + 0x3f08)

#define   CG3DDISHRS_CLKGATE_DIS               REG_BIT(5)



#define VDBOX_CGCTL3F10(base)			XE_REG((base) + 0x3f10)

#define   IECPUNIT_CLKGATE_DIS			REG_BIT(22)

drivers/gpu/drm/xe/xe_wa.c

+5 −0
Original line number Diff line number Diff line
@@ -287,6 +287,11 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("14019449301"),

	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},



	{}

};