Commit 8c251c5a authored by Li Ming's avatar Li Ming Committed by Dave Jiang
Browse files

cxl/pci: Get AER capability address from RCRB only for RCH dport 



cxl_setup_parent_dport() needs to get RCH dport AER capability address
from RCRB to disable AER interrupt. The function does not check if dport
is RCH dport, it will get a wrong pci_host_bridge structure by dport_dev
in VH case because dport_dev points to a pci device(RP or switch DSP)
rather than a pci host bridge device.

Fixes: f05fd10d ("cxl/pci: Add RCH downstream port AER register discovery")
Signed-off-by: default avatarLi Ming <ming4.li@intel.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Tested-by: default avatarIra Weiny <ira.weiny@intel.com>
Tested-by: default avatarAlison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240809082750.3015641-2-ming4.li@intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent de9c2c66

drivers/cxl/core/pci.c

+6 −4
Original line number Diff line number Diff line
@@ -834,11 +834,13 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) 
void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)

{

	struct device *dport_dev = dport->dport_dev;

	struct pci_host_bridge *host_bridge;



	host_bridge = to_pci_host_bridge(dport_dev);

	if (dport->rch) {

		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev);



		if (host_bridge->native_aer)

			dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);

	}



	dport->reg_map.host = host;

	cxl_dport_map_regs(dport);