Commit 8c2d61e0 authored by Matthew Auld's avatar Matthew Auld
Browse files

drm/xe/migrate: don't overflow max copy size 



With non-page aligned copy, we need to use 4 byte aligned pitch, however
the size itself might still be close to our maximum of ~8M, and so the
dimensions of the copy can easily exceed the S16_MAX limit of the copy
command leading to the following assert:

xe 0000:03:00.0: [drm] Assertion `size / pitch <= ((s16)(((u16)~0U) >> 1))` failed!
platform: BATTLEMAGE subplatform: 1
graphics: Xe2_HPG 20.01 step A0
media: Xe2_HPM 13.01 step A1
tile: 0 VRAM 10.0 GiB
GT: 0 type 1

WARNING: CPU: 23 PID: 10605 at drivers/gpu/drm/xe/xe_migrate.c:673 emit_copy+0x4b5/0x4e0 [xe]

To fix this account for the pitch when calculating the number of current
bytes to copy.

Fixes: 270172f6 ("drm/xe: Update xe_ttm_access_memory to use GPU for non-visible access")
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Maciej Patelczyk <maciej.patelczyk@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarStuart Summers <stuart.summers@intel.com>
Link: https://lore.kernel.org/r/20250731093807.207572-7-matthew.auld@intel.com
parent 38b34e92

drivers/gpu/drm/xe/xe_migrate.c

+6 −0
Original line number Diff line number Diff line
@@ -2084,6 +2084,12 @@ int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo, 
		else

			current_bytes = min_t(int, bytes_left, cursor.size);



		if (current_bytes & ~PAGE_MASK) {

			int pitch = 4;



			current_bytes = min_t(int, current_bytes, S16_MAX * pitch);

		}



		if (fence)

			dma_fence_put(fence);