Commit 8c711ff3 authored by Jagan Teki's avatar Jagan Teki Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH 



Edgeble NCM6A-IO board has 2.5Gbps Ethernet via PCI2_0.

Add support for it.

Signed-off-by: default avatarJagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20231125190522.87607-7-jagan@edgeble.ai


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9f6d8911

arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -3,16 +3,31 @@ 
 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.

 */



#include <dt-bindings/gpio/gpio.h>



/ {

	chosen {

		stdout-path = "serial2:1500000n8";

	};



	vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc3v3_pcie2x1l0";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		startup-delay-us = <5000>;

		vin-supply = <&vcc_3v3_s3>;

	};

};



&combphy0_ps {

	status = "okay";

};



&combphy1_ps {

	status = "okay";

};



&i2c6 {

	status = "okay";
@@ -29,7 +44,22 @@ hym8563: rtc@51 { 
	};

};



/* ETH */

&pcie2x1l0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie2_0_rst>;

	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */

	vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;

	status = "okay";

};



&pinctrl {

	pcie2 {

		pcie2_0_rst: pcie2-0-rst {

			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	hym8563 {

		hym8563_int: hym8563-int {

			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;