Commit 8c72b2a2 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
ice: remaining TSPLL cleanups

These are the remaining patches from the "ice: Separate TSPLL from PTP
and cleanup" series [1] with control flow macros removed. What remains
are cleanups and some minor improvements.

[1] https://lore.kernel.org/netdev/20250618174231.3100231-1-anthony.l.nguyen@intel.com/

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  ice: default to TIME_REF instead of TXCO on E825-C
  ice: move TSPLL init calls to ice_ptp.c
  ice: fall back to TCXO on TSPLL lock fail
  ice: wait before enabling TSPLL
  ice: add multiple TSPLL helpers
  ice: use bitfields instead of unions for CGU regs
  ice: read TSPLL registers again before reporting status
  ice: clear time_sync_en field for E825-C during reprogramming
====================

Link: https://patch.msgid.link/20250626162921.1173068-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents f7dbedba 8b498754

drivers/net/ethernet/intel/ice/ice_common.c

+1 −1
Original line number Diff line number Diff line
@@ -2302,7 +2302,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);

	} else {

		info->clk_freq = ICE_TSPLL_FREQ_156_250;

		info->clk_src = ICE_CLK_SRC_TCXO;

		info->clk_src = ICE_CLK_SRC_TIME_REF;

	}



	if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {

drivers/net/ethernet/intel/ice/ice_common.h

+32 −180
Original line number Diff line number Diff line
@@ -40,193 +40,45 @@ 
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)



#define ICE_CGU_R9			0x24

union ice_cgu_r9 {

	struct {

		u32 time_ref_freq_sel : 3;

		u32 clk_eref1_en : 1;

		u32 clk_eref0_en : 1;

		u32 time_ref_en : 1;

		u32 time_sync_en : 1;

		u32 one_pps_out_en : 1;

		u32 clk_ref_synce_en : 1;

		u32 clk_synce1_en : 1;

		u32 clk_synce0_en : 1;

		u32 net_clk_ref1_en : 1;

		u32 net_clk_ref0_en : 1;

		u32 clk_synce1_amp : 2;

		u32 misc6 : 1;

		u32 clk_synce0_amp : 2;

		u32 one_pps_out_amp : 2;

		u32 misc24 : 12;

	};

	u32 val;

};

#define ICE_CGU_R9_TIME_REF_FREQ_SEL	GENMASK(2, 0)

#define ICE_CGU_R9_CLK_EREF0_EN		BIT(4)

#define ICE_CGU_R9_TIME_REF_EN		BIT(5)

#define ICE_CGU_R9_TIME_SYNC_EN		BIT(6)

#define ICE_CGU_R9_ONE_PPS_OUT_EN	BIT(7)

#define ICE_CGU_R9_ONE_PPS_OUT_AMP	GENMASK(19, 18)



#define ICE_CGU_R16			0x40

union ice_cgu_r16 {

	struct {

		u32 synce_remndr : 6;

		u32 synce_phlmt_en : 1;

		u32 misc13 : 17;

		u32 ck_refclkfreq : 8;

	};

	u32 val;

};

#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ	GENMASK(31, 24)



#define ICE_CGU_R19 0x4c

union ice_cgu_r19_e82x {

	struct {

		u32 fbdiv_intgr : 8;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 3;

		u32 ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;

		u32 japll_iref_ndivratio : 3;

		u32 misc27 : 1;

	};

	u32 val;

};



union ice_cgu_r19_e825 {

	struct {

		u32 tspll_fbdiv_intgr : 10;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 1;

		u32 tspll_ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;

		u32 japll_postdiv_pdivratio : 3;

		u32 misc27 : 1;

	};

	u32 val;

};

#define ICE_CGU_R19			0x4C

#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X	GENMASK(7, 0)

#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825	GENMASK(9, 0)

#define ICE_CGU_R19_TSPLL_NDIVRATIO	GENMASK(19, 16)



#define ICE_CGU_R22			0x58

union ice_cgu_r22 {

	struct {

		u32 fdpll_frac_div_out_nc : 2;

		u32 fdpll_lock_int_for : 1;

		u32 synce_hdov_int_for : 1;

		u32 synce_lock_int_for : 1;

		u32 fdpll_phlead_slip_nc : 1;

		u32 fdpll_acc1_ovfl_nc : 1;

		u32 fdpll_acc2_ovfl_nc : 1;

		u32 synce_status_nc : 6;

		u32 fdpll_acc1f_ovfl : 1;

		u32 misc18 : 1;

		u32 fdpllclk_div : 4;

		u32 time1588clk_div : 4;

		u32 synceclk_div : 4;

		u32 synceclk_sel_div2 : 1;

		u32 fdpllclk_sel_div2 : 1;

		u32 time1588clk_sel_div2 : 1;

		u32 misc3 : 1;

	};

	u32 val;

};

#define ICE_CGU_R22_TIME1588CLK_DIV	GENMASK(23, 20)

#define ICE_CGU_R22_TIME1588CLK_DIV2	BIT(30)



#define ICE_CGU_R23			0x5C

union ice_cgu_r23 {

	struct {

		u32 cgupll_fbdiv_intgr : 10;

		u32 ux56pll_fbdiv_intgr : 10;

		u32 misc20 : 4;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;



	};

	u32 val;

};



#define ICE_CGU_R24			0x60

union ice_cgu_r24 {

	struct {

		u32 fbdiv_frac : 22;

		u32 misc20 : 2;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;

	};

	u32 val;

};

#define ICE_CGU_R24_FBDIV_FRAC		GENMASK(21, 0)

#define ICE_CGU_R23_R24_TSPLL_ENABLE	BIT(24)

#define ICE_CGU_R23_R24_REF1588_CK_DIV	GENMASK(30, 27)

#define ICE_CGU_R23_R24_TIME_REF_SEL	BIT(31)



#define TSPLL_CNTR_BIST_SETTINGS 0x344

union tspll_cntr_bist_settings {

	struct {

		u32 i_irefgen_settling_time_cntr_7_0 : 8;

		u32 i_irefgen_settling_time_ro_standby_1_0 : 2;

		u32 reserved195 : 5;

		u32 i_plllock_sel_0 : 1;

		u32 i_plllock_sel_1 : 1;

		u32 i_plllock_cnt_6_0 : 7;

		u32 i_plllock_cnt_10_7 : 4;

		u32 reserved200 : 4;

	};

	u32 val;

};

#define ICE_CGU_BW_TDC			0x31C

#define ICE_CGU_BW_TDC_PLLLOCK_SEL	GENMASK(30, 29)



#define TSPLL_RO_BWM_LF 0x370

union tspll_ro_bwm_lf {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 biascaldone_cri : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 m2fbdivmod_cri_7_0 : 8;

	};

	u32 val;

};

#define ICE_CGU_RO_LOCK			0x3F0

#define ICE_CGU_RO_LOCK_TRUE_LOCK	BIT(12)

#define ICE_CGU_RO_LOCK_UNLOCK		BIT(13)



#define TSPLL_RO_LOCK_E825C 0x3f0

union tspll_ro_lock_e825c {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 reserved455 : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 reserved462 : 8;

	};

	u32 val;

};

#define ICE_CGU_CNTR_BIST		0x344

#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0	BIT(15)

#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1	BIT(16)



#define TSPLL_BW_TDC_E825C 0x31c

union tspll_bw_tdc_e825c {

	struct {

		u32 i_tdc_offset_lock_1_0 : 2;

		u32 i_bbthresh1_2_0 : 3;

		u32 i_bbthresh2_2_0 : 3;

		u32 i_tdcsel_1_0 : 2;

		u32 i_tdcovccorr_en_h : 1;

		u32 i_divretimeren : 1;

		u32 i_bw_ampmeas_window : 1;

		u32 i_bw_lowerbound_2_0 : 3;

		u32 i_bw_upperbound_2_0 : 3;

		u32 i_bw_mode_1_0 : 2;

		u32 i_ft_mode_sel_2_0 : 3;

		u32 i_bwphase_4_0 : 5;

		u32 i_plllock_sel_1_0 : 2;

		u32 i_afc_divratio : 1;

	};

	u32 val;

};

#define ICE_CGU_RO_BWM_LF		0x370

#define ICE_CGU_RO_BWM_LF_TRUE_LOCK	BIT(12)



int ice_init_hw(struct ice_hw *hw);

void ice_deinit_hw(struct ice_hw *hw);

drivers/net/ethernet/intel/ice/ice_ptp.c

+11 −0
Original line number Diff line number Diff line
@@ -2892,6 +2892,10 @@ static int ice_ptp_rebuild_owner(struct ice_pf *pf) 
	if (err)

		return err;



	err = ice_tspll_init(hw);

	if (err)

		return err;



	/* Acquire the global hardware lock */

	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;
@@ -3059,6 +3063,13 @@ static int ice_ptp_init_owner(struct ice_pf *pf) 
		return err;

	}



	err = ice_tspll_init(hw);

	if (err) {

		dev_err(ice_pf_to_dev(pf), "Failed to initialize CGU, status %d\n",

			err);

		return err;

	}



	/* Acquire the global hardware lock */

	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+1 −21
Original line number Diff line number Diff line
@@ -2115,20 +2115,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 
	return 0;

}



/**

 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization

 * @hw: pointer to HW struct

 *

 * Perform E825-specific PTP hardware clock initialization steps.

 *

 * Return: 0 on success, negative error code otherwise.

 */

static int ice_ptp_init_phc_e825(struct ice_hw *hw)

{

	/* Initialize the Clock Generation Unit */

	return ice_tspll_init(hw);

}



/**

 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status

 * @hw: pointer to the HW struct
@@ -2788,7 +2774,6 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 
 */

static int ice_ptp_init_phc_e82x(struct ice_hw *hw)

{

	int err;

	u32 val;



	/* Enable reading switch and PHY registers over the sideband queue */
@@ -2798,11 +2783,6 @@ static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 
	val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);

	wr32(hw, PF_SB_REM_DEV_CTL, val);



	/* Initialize the Clock Generation Unit */

	err = ice_tspll_init(hw);

	if (err)

		return err;



	/* Set window length for all the ports */

	return ice_ptp_set_vernier_wl(hw);

}
@@ -5584,7 +5564,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) 
	case ICE_MAC_GENERIC:

		return ice_ptp_init_phc_e82x(hw);

	case ICE_MAC_GENERIC_3K_E825:

		return ice_ptp_init_phc_e825(hw);

		return 0;

	default:

		return -EOPNOTSUPP;

	}

drivers/net/ethernet/intel/ice/ice_tspll.c

+271 −156

File changed.

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