Commit 8c82bfdd authored by Daniel Machon's avatar Daniel Machon Committed by David S. Miller
Browse files

net: sparx5: add new register definitions 



In preparation for port mirroring support through tc matchall, add the
required register definitions.

Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Reviewed-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a2d2cadc

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

+68 −0
Original line number Diff line number Diff line
@@ -83,6 +83,64 @@ enum sparx5_target { 
#define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\

	FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)



/*      ANA_AC:MIRROR_PROBE:PROBE_CFG */

#define ANA_AC_PROBE_CFG(g) \

	__REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4)



#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27)

#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)

#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)



#define ANA_AC_PROBE_CFG_PROBE_CPU_SET      GENMASK(26, 19)

#define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)

#define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)



#define ANA_AC_PROBE_CFG_PROBE_VID          GENMASK(18, 6)

#define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)

#define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x)



#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE    GENMASK(5, 4)

#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)

#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)



#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE     GENMASK(3, 2)

#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)

#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)



#define ANA_AC_PROBE_CFG_PROBE_DIRECTION    GENMASK(1, 0)

#define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)

#define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\

	FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)



/*      ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */

#define ANA_AC_PROBE_PORT_CFG(g) \

	__REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4)



/*      ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */

#define ANA_AC_PROBE_PORT_CFG1(g) \

	__REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4)



/*      ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */

#define ANA_AC_PROBE_PORT_CFG2(g) \

	__REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4)



#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0)

#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\

	FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)

#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\

	FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)



/*      ANA_AC:SRC:SRC_CFG */

#define ANA_AC_SRC_CFG(g)         __REG(TARGET_ANA_AC,\

					0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
@@ -6203,6 +6261,16 @@ enum sparx5_target { 
#define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\

	FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)



/*      QFWD:SYSTEM:FRAME_COPY_CFG */

#define QFWD_FRAME_COPY_CFG(r)\

	__REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4)



#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL   GENMASK(12, 6)

#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\

	FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)

#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\

	FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)



/*      QRES:RES_CTRL:RES_CFG */

#define QRES_RES_CFG(g)           __REG(TARGET_QRES,\

					0, 1, 0, g, 5120, 16, 0, 0, 1, 4)