Unverified Commit 8c87a46e authored by Thierry Reding's avatar Thierry Reding Committed by Mark Brown
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dt-bindings: spi: tegra-slink: Convert to json-schema 



Convert the Tegra SLINK bindings from the free-form text format to
json-schema.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230705152603.2514235-1-thierry.reding@gmail.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4f81b540

Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt

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NVIDIA Tegra20/Tegra30 SLINK controller.



Required properties:

- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".

- reg: Should contain SLINK registers location and length.

- interrupts: Should contain SLINK interrupts.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.

- resets : Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names : Must include the following entries:

  - spi

- dmas : Must contain an entry for each entry in clock-names.

  See ../dma/dma.txt for details.

- dma-names : Must include the following entries:

  - rx

  - tx



Recommended properties:

- spi-max-frequency: Definition as per

                     Documentation/devicetree/bindings/spi/spi-bus.txt



Example:



spi@7000d600 {

	compatible = "nvidia,tegra20-slink";

	reg = <0x7000d600 0x200>;

	interrupts = <0 82 0x04>;

	spi-max-frequency = <25000000>;

	#address-cells = <1>;

	#size-cells = <0>;

	clocks = <&tegra_car 44>;

	resets = <&tegra_car 44>;

	reset-names = "spi";

	dmas = <&apbdma 16>, <&apbdma 16>;

	dma-names = "rx", "tx";

};

Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra20/30 SLINK controller



maintainers:

  - Thierry Reding <thierry.reding@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>



properties:

  compatible:

    enum:

      - nvidia,tegra20-slink

      - nvidia,tegra30-slink



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: module clock



  resets:

    items:

      - description: module reset



  reset-names:

    items:

      - const: spi



  dmas:

    items:

      - description: DMA channel used for reception

      - description: DMA channel used for transmission



  dma-names:

    items:

      - const: rx

      - const: tx



  operating-points-v2:

    $ref: /schemas/types.yaml#/definitions/phandle



  power-domains:

    items:

      - description: phandle to the core power domain



  spi-max-frequency:

    description: Maximum SPI clocking speed of the controller in Hz.

    $ref: /schemas/types.yaml#/definitions/uint32



allOf:

  - $ref: spi-controller.yaml



unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - resets

  - reset-names

  - dmas

  - dma-names



examples:

  - |

    #include <dt-bindings/clock/tegra20-car.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    spi@7000d600 {

        compatible = "nvidia,tegra20-slink";

        reg = <0x7000d600 0x200>;

        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

        spi-max-frequency = <25000000>;

        #address-cells = <1>;

        #size-cells = <0>;

        clocks = <&tegra_car TEGRA20_CLK_SBC2>;

        resets = <&tegra_car 44>;

        reset-names = "spi";

        dmas = <&apbdma 16>, <&apbdma 16>;

        dma-names = "rx", "tx";

    };