Commit 8c993dad authored by Clay King's avatar Clay King Committed by Alex Deucher
Browse files

drm/amd/display: Clean up unused code



[WHAT]
Silence warning by cleaning up unused code.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarClay King <clayking@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 41a5b623
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+1 −0
Original line number Diff line number Diff line
@@ -547,6 +547,7 @@ void dcn3_clk_mgr_construct(
	/* in case we don't get a value from the register, use default */
	if (clk_mgr->base.dentist_vco_freq_khz == 0)
		clk_mgr->base.dentist_vco_freq_khz = 3650000;

	/* Convert dprefclk units from MHz to KHz */
	/* Value already divided by 10, some resolution lost */

+0 −1
Original line number Diff line number Diff line
@@ -2431,7 +2431,6 @@ static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,

	int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
	bool is_primary;
	DC_LOGGER_INIT(dc->ctx->logger);

	slice_count = resource_get_opp_heads_for_otg_master(otg_master,
			&state->res_ctx, opp_heads);
+2 −2
Original line number Diff line number Diff line
@@ -23,8 +23,8 @@

#include "amdgpu_dm_trace.h"

#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \
	for (index = 0; index < max_pipes; ++index) { \
#define TRACE_DC_PIPE_STATE(pipe_ctx, max_pipes) \
	for (int index = 0; index < max_pipes; ++index) { \
		struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \
		if (pipe_ctx->plane_state) \
			trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
+0 −4
Original line number Diff line number Diff line
@@ -1151,8 +1151,6 @@ void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_siz
{
	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);

	unsigned int cur_compbuf_size_seg = 0;

	if (safe_to_increase || compbuf_size_seg <= hubbub2->compbuf_size_segments) {
		if (compbuf_size_seg > hubbub2->compbuf_size_segments) {
			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
@@ -1165,8 +1163,6 @@ void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_siz
				+ hubbub2->det3_size + compbuf_size_seg <= hubbub2->crb_size_segs);
		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_seg);
		hubbub2->compbuf_size_segments = compbuf_size_seg;

		ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &cur_compbuf_size_seg) && !cur_compbuf_size_seg);
	}
}

+12 −12
Original line number Diff line number Diff line
@@ -86,9 +86,9 @@
	hws->ctx

#define DC_LOGGER \
	ctx->logger
#define DC_LOGGER_INIT() \
	struct dc_context *ctx = dc->ctx
	dc_ctx->logger
#define DC_LOGGER_INIT(ctx) \
	struct dc_context *dc_ctx = ctx

#define REG(reg)\
	hws->regs->reg
@@ -687,7 +687,7 @@ dce110_external_encoder_control(enum bp_external_encoder_control_action action,
		.pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
		.color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888,
	};
	DC_LOGGER_INIT();
	DC_LOGGER_INIT(dc->ctx);

	bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl);

@@ -767,13 +767,14 @@ void dce110_edp_wait_for_hpd_ready(
		struct dc_link *link,
		bool power_up)
{
	struct dc_context *ctx = link->ctx;
	struct graphics_object_id connector = link->link_enc->connector;
	bool edp_hpd_high = false;
	uint32_t time_elapsed = 0;
	uint32_t timeout = power_up ?
		PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;

	DC_LOGGER_INIT(link->ctx);

	if (dal_graphics_object_id_get_connector_id(connector)
			!= CONNECTOR_ID_EDP) {
		BREAK_TO_DEBUGGER();
@@ -825,6 +826,7 @@ void dce110_edp_power_control(
	enum bp_result bp_result;
	uint8_t pwrseq_instance;

	DC_LOGGER_INIT(ctx);

	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
			!= CONNECTOR_ID_EDP) {
@@ -993,6 +995,8 @@ void dce110_edp_backlight_control(
	unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0);
	unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0);

	DC_LOGGER_INIT(ctx);

	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
		!= CONNECTOR_ID_EDP) {
		BREAK_TO_DEBUGGER();
@@ -1969,8 +1973,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
	bool keep_edp_vdd_on = false;
	bool should_clean_dsc_block = true;
	struct dc_bios *dcb = dc->ctx->dc_bios;
	DC_LOGGER_INIT();

	DC_LOGGER_INIT(dc->ctx);

	get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
	dc_get_edp_links(dc, edp_links, &edp_num);
@@ -2736,7 +2739,6 @@ static bool wait_for_reset_trigger_to_occur(
	struct dc_context *dc_ctx,
	struct timing_generator *tg)
{
	struct dc_context *ctx = dc_ctx;
	bool rc = false;

	/* To avoid endless loop we wait at most
@@ -2778,10 +2780,9 @@ static void dce110_enable_timing_synchronization(
		int group_size,
		struct pipe_ctx *grouped_pipes[])
{
	struct dc_context *dc_ctx = dc->ctx;
	struct dcp_gsl_params gsl_params = { 0 };
	int i;
	DC_LOGGER_INIT();
	DC_LOGGER_INIT(dc->ctx);

	DC_SYNC_INFO("GSL: Setting-up...\n");

@@ -2824,10 +2825,9 @@ static void dce110_enable_per_frame_crtc_position_reset(
		int group_size,
		struct pipe_ctx *grouped_pipes[])
{
	struct dc_context *dc_ctx = dc->ctx;
	struct dcp_gsl_params gsl_params = { 0 };
	int i;
	DC_LOGGER_INIT();
	DC_LOGGER_INIT(dc->ctx);

	gsl_params.gsl_group = 0;
	gsl_params.gsl_master = 0;
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