Commit 8cc14fdc authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/amuv1-avg-freq', 'for-next/pkey_unrestricted',... 

Merge branches 'for-next/amuv1-avg-freq', 'for-next/pkey_unrestricted', 'for-next/sysreg', 'for-next/misc', 'for-next/pgtable-cleanups', 'for-next/kselftest', 'for-next/uaccess-mops', 'for-next/pie-poe-cleanup', 'for-next/cputype-kryo', 'for-next/cca-dma-address', 'for-next/drop-pxd_table_bit' and 'for-next/spectre-bhb-assume-vulnerable', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf:
  perf/arm_cspmu: Fix missing io.h include
  perf/arm_cspmu: Add PMEVFILT2R support
  perf/arm_cspmu: Generalise event filtering
  perf/arm_cspmu: Move register definitons to header
  drivers/perf: apple_m1: Support host/guest event filtering
  drivers/perf: apple_m1: Refactor event select/filter configuration
  perf/dwc_pcie: fix duplicate pci_dev devices
  perf/dwc_pcie: fix some unreleased resources
  perf/arm-cmn: Minor event type housekeeping
  perf: arm_pmu: Move PMUv3-specific data
  perf: apple_m1: Don't disable counter in m1_pmu_enable_event()
  perf: arm_v7_pmu: Don't disable counter in (armv7|krait_|scorpion_)pmu_enable_event()
  perf: arm_v7_pmu: Drop obvious comments for enabling/disabling counters and interrupts
  perf: arm_pmuv3: Don't disable counter in armv8pmu_enable_event()
  perf: arm_pmu: Don't disable counter in armpmu_add()
  perf: arm_pmuv3: Call kvm_vcpu_pmu_resync_el0() before enabling counters
  perf: arm_pmuv3: Add support for ARM Rainier PMU

* for-next/amuv1-avg-freq:
  : Add support for AArch64 AMUv1-based average freq
  arm64: Utilize for_each_cpu_wrap for reference lookup
  arm64: Update AMU-based freq scale factor on entering idle
  arm64: Provide an AMU-based version of arch_freq_get_on_cpu
  cpufreq: Introduce an optional cpuinfo_avg_freq sysfs entry
  cpufreq: Allow arch_freq_get_on_cpu to return an error
  arch_topology: init capacity_freq_ref to 0

* for-next/pkey_unrestricted:
  : mm/pkey: Add PKEY_UNRESTRICTED macro
  selftest/powerpc/mm/pkey: fix build-break introduced by commit 00894c3f
  selftests/powerpc: Use PKEY_UNRESTRICTED macro
  selftests/mm: Use PKEY_UNRESTRICTED macro
  mm/pkey: Add PKEY_UNRESTRICTED macro

* for-next/sysreg:
  : arm64 sysreg updates
  arm64/sysreg: Enforce whole word match for open/close tokens
  arm64/sysreg: Fix unbalanced closing block
  arm64/sysreg: Add register fields for HFGWTR2_EL2
  arm64/sysreg: Add register fields for HFGRTR2_EL2
  arm64/sysreg: Add register fields for HFGITR2_EL2
  arm64/sysreg: Add register fields for HDFGWTR2_EL2
  arm64/sysreg: Add register fields for HDFGRTR2_EL2
  arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1

* for-next/misc:
  : Miscellaneous arm64 patches
  arm64: mm: Don't use %pK through printk
  arm64/fpsimd: Remove unused declaration fpsimd_kvm_prepare()

* for-next/pgtable-cleanups:
  : arm64 pgtable accessors cleanup
  arm64/mm: Define PTDESC_ORDER
  arm64/kernel: Always use level 2 or higher for early mappings
  arm64/hugetlb: Consistently use pud_sect_supported()
  arm64/mm: Convert __pte_to_phys() and __phys_to_pte_val() as functions

* for-next/kselftest:
  : arm64 kselftest updates
  kselftest/arm64: mte: Skip the hugetlb tests if MTE not supported on such mappings
  kselftest/arm64: mte: Use the correct naming for tag check modes in check_hugetlb_options.c

* for-next/uaccess-mops:
  : Implement the uaccess memory copy/set using MOPS instructions
  arm64: lib: Use MOPS for usercopy routines
  arm64: mm: Handle PAN faults on uaccess CPY* instructions
  arm64: extable: Add fixup handling for uaccess CPY* instructions

* for-next/pie-poe-cleanup:
  : PIE/POE helpers cleanup
  arm64/sysreg: Move POR_EL0_INIT to asm/por.h
  arm64/sysreg: Rename POE_RXW to POE_RWX
  arm64/sysreg: Improve PIR/POR helpers

* for-next/cputype-kryo:
  : Add cputype info for some Qualcomm Kryo cores
  arm64: cputype: Add comments about Qualcomm Kryo 5XX and 6XX cores
  arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD

* for-next/cca-dma-address:
  : Fix DMA address for devices used in realms with Arm CCA
  arm64: realm: Use aliased addresses for device DMA to shared buffers
  dma: Introduce generic dma_addr_*crypted helpers
  dma: Fix encryption bit clearing for dma_to_phys

* for-next/drop-pxd_table_bit:
  : Drop the arm64 PXD_TABLE_BIT (clean-up in preparation for 128-bit PTEs)
  arm64/mm: Drop PXD_TABLE_BIT
  arm64/mm: Check pmd_table() in pmd_trans_huge()
  arm64/mm: Check PUD_TYPE_TABLE in pud_bad()
  arm64/mm: Check PXD_TYPE_TABLE in [p4d|pgd]_bad()
  arm64/mm: Clear PXX_TYPE_MASK and set PXD_TYPE_SECT in [pmd|pud]_mkhuge()
  arm64/mm: Clear PXX_TYPE_MASK in mk_[pmd|pud]_sect_prot()
  arm64/ptdump: Test PMD_TYPE_MASK for block mapping
  KVM: arm64: ptdump: Test PMD_TYPE_MASK for block mapping

* for-next/spectre-bhb-assume-vulnerable:
  : Rework Spectre BHB mitigations to not assume "safe"
  arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists
  arm64: cputype: Add MIDR_CORTEX_A76AE
  arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list
  arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB
  arm64: errata: Add QCOM_KRYO_4XX_GOLD to the spectre_bhb_k24_list
parents 9651f789 20711efa 73276cee 2fdbf2ff 892d20ac 51ecb29f 306219d5 fe59e035 650701e4 53a52a0e 7d953a06 50c27266 a5951389

Documentation/admin-guide/pm/cpufreq.rst

+16 −1
Original line number Diff line number Diff line
@@ -248,6 +248,20 @@ are the following: 
	If that frequency cannot be determined, this attribute should not

	be present.



``cpuinfo_avg_freq``

        An average frequency (in KHz) of all CPUs belonging to a given policy,

        derived from a hardware provided feedback and reported on a time frame

        spanning at most few milliseconds.



        This is expected to be based on the frequency the hardware actually runs

        at and, as such, might require specialised hardware support (such as AMU

        extension on ARM). If one cannot be determined, this attribute should

        not be present.



        Note, that failed attempt to retrieve current frequency for a given

        CPU(s) will result in an appropriate error, i.e: EAGAIN for CPU that

        remains idle (raised on ARM).



``cpuinfo_max_freq``

	Maximum possible operating frequency the CPUs belonging to this policy

	can run at (in kHz).
@@ -293,7 +307,8 @@ are the following: 
	Some architectures (e.g. ``x86``) may attempt to provide information

	more precisely reflecting the current CPU frequency through this

	attribute, but that still may not be the exact current CPU frequency as

	seen by the hardware at the moment.

	seen by the hardware at the moment. This behavior though, is only

	available via c:macro:``CPUFREQ_ARCH_CUR_FREQ`` option.



``scaling_driver``

	The scaling driver currently in use.

arch/arm64/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ config ARCH_MMAP_RND_BITS_MIN 
	default 18



# max bits determined by the following formula:

#  VA_BITS - PAGE_SHIFT - 3

#  VA_BITS - PTDESC_TABLE_SHIFT

config ARCH_MMAP_RND_BITS_MAX

	default 19 if ARM64_VA_BITS=36

	default 24 if ARM64_VA_BITS=39

arch/arm64/include/asm/asm-extable.h

+9 −1
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ 
#define EX_TYPE_BPF			1

#define EX_TYPE_UACCESS_ERR_ZERO	2

#define EX_TYPE_KACCESS_ERR_ZERO	3

#define EX_TYPE_LOAD_UNALIGNED_ZEROPAD	4

#define EX_TYPE_UACCESS_CPY		4

#define EX_TYPE_LOAD_UNALIGNED_ZEROPAD	5



/* Data fields for EX_TYPE_UACCESS_ERR_ZERO */

#define EX_DATA_REG_ERR_SHIFT	0
@@ -23,6 +24,9 @@ 
#define EX_DATA_REG_ADDR_SHIFT	5

#define EX_DATA_REG_ADDR	GENMASK(9, 5)



/* Data fields for EX_TYPE_UACCESS_CPY */

#define EX_DATA_UACCESS_WRITE	BIT(0)



#ifdef __ASSEMBLY__



#define __ASM_EXTABLE_RAW(insn, fixup, type, data)	\
@@ -69,6 +73,10 @@ 
	.endif

	.endm



	.macro		_asm_extable_uaccess_cpy, insn, fixup, uaccess_is_write

	__ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_UACCESS_CPY, \uaccess_is_write)

	.endm



#else /* __ASSEMBLY__ */



#include <linux/stringify.h>

arch/arm64/include/asm/asm-uaccess.h

+4 −0
Original line number Diff line number Diff line
@@ -61,6 +61,10 @@ alternative_else_nop_endif 
9999:	x;					\

	_asm_extable_uaccess	9999b, l



#define USER_CPY(l, uaccess_is_write, x...)	\

9999:	x;					\

	_asm_extable_uaccess_cpy 9999b, l, uaccess_is_write



/*

 * Generate the assembly for LDTR/STTR with exception table entries.

 * This is complicated as there is no post-increment or pair versions of the

arch/arm64/include/asm/cputype.h

+14 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ 
#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A76AE	0xD0E

#define ARM_CPU_PART_NEOVERSE_V1	0xD40

#define ARM_CPU_PART_CORTEX_A78		0xD41

#define ARM_CPU_PART_CORTEX_A78AE	0xD42
@@ -119,6 +120,7 @@ 
#define QCOM_CPU_PART_KRYO		0x200

#define QCOM_CPU_PART_KRYO_2XX_GOLD	0x800

#define QCOM_CPU_PART_KRYO_2XX_SILVER	0x801

#define QCOM_CPU_PART_KRYO_3XX_GOLD	0x802

#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803

#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804

#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805
@@ -159,6 +161,7 @@ 
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A76AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76AE)

#define MIDR_NEOVERSE_V1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)

#define MIDR_CORTEX_A78	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)

#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
@@ -196,10 +199,21 @@ 
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)

#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)

#define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD)

#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)

#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)

#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)

#define MIDR_QCOM_ORYON_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_ORYON_X1)



/*

 * NOTES:

 * - Qualcomm Kryo 5XX Prime / Gold ID themselves as MIDR_CORTEX_A77

 * - Qualcomm Kryo 5XX Silver IDs itself as MIDR_QCOM_KRYO_4XX_SILVER

 * - Qualcomm Kryo 6XX Prime IDs itself as MIDR_CORTEX_X1

 * - Qualcomm Kryo 6XX Gold IDs itself as ARM_CPU_PART_CORTEX_A78

 * - Qualcomm Kryo 6XX Silver IDs itself as MIDR_CORTEX_A55

 */



#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)