Commit 8cc41023 authored by Daniel Machon's avatar Daniel Machon Committed by Paolo Abeni
Browse files

net: sparx5: redefine internal ports and PGID's as offsets 



Internal ports and PGID's are both defined relative to the number of
front ports on Sparx5. This will not work on lan969x. Instead make them
offsets to the number of front ports and add two helpers to retrieve
them. Use the helpers throughout.

Reviewed-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 4b67bcb9

drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c

+10 −4
Original line number Diff line number Diff line
@@ -118,16 +118,22 @@ static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, 


	if (portno >= sparx5->data->consts->n_ports) {

		/* Internal ports */

		if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) {

		if (portno ==

			    sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) ||

		    portno ==

			    sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) {

			/* Equals 1.25G */

			return SPX5_CAL_SPEED_2G5;

		} else if (portno == SPX5_PORT_VD0) {

		} else if (portno ==

			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) {

			/* IPMC only idle BW */

			return SPX5_CAL_SPEED_NONE;

		} else if (portno == SPX5_PORT_VD1) {

		} else if (portno ==

			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) {

			/* OAM only idle BW */

			return SPX5_CAL_SPEED_NONE;

		} else if (portno == SPX5_PORT_VD2) {

		} else if (portno ==

			   sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) {

			/* IPinIP gets only idle BW */

			return SPX5_CAL_SPEED_NONE;

		}

drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c

+3 −1
Original line number Diff line number Diff line
@@ -364,7 +364,9 @@ static void sparx5_fdma_injection_mode(struct sparx5 *sparx5) 
		sparx5, QS_INJ_GRP_CFG(INJ_QUEUE));



	/* CPU ports capture setup */

	for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) {

	for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0);

	     portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1);

	     portno++) {

		/* ASM CPU port: No preamble, IFH, enable padding */

		spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) |

			ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |

drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c

+2 −1
Original line number Diff line number Diff line
@@ -129,7 +129,8 @@ int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr) 
	struct sparx5_port *port = netdev_priv(dev);

	struct sparx5 *sparx5 = port->sparx5;



	return sparx5_mact_learn(sparx5, PGID_CPU, addr, port->pvid);

	return sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU),

				 addr, port->pvid);

}



static int sparx5_mact_get(struct sparx5 *sparx5,

drivers/net/ethernet/microchip/sparx5/sparx5_main.c

+8 −6
Original line number Diff line number Diff line
@@ -649,13 +649,14 @@ static int sparx5_start(struct sparx5 *sparx5) 
	sparx5_update_fwd(sparx5);



	/* CPU copy CPU pgids */

	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),

		sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU));

	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),

		sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST));

	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,

		ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU)));

	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,

		ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST)));



	/* Recalc injected frame FCS */

	for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++)

	for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0);

	     idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++)

		spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),

			 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,

			 sparx5, ANA_CL_FILTER_CTRL(idx));
@@ -670,7 +671,8 @@ static int sparx5_start(struct sparx5 *sparx5) 
	sparx5_vlan_init(sparx5);



	/* Add host mode BC address (points only to CPU) */

	sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID);

	sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast,

			  NULL_VID);



	/* Enable queue limitation watermarks */

	sparx5_qlim_set(sparx5);

drivers/net/ethernet/microchip/sparx5/sparx5_main.h

+17 −17
Original line number Diff line number Diff line
@@ -54,23 +54,21 @@ enum sparx5_vlan_port_type { 
#define SPX5_PORTS             65

#define SPX5_PORTS_ALL         70 /* Total number of ports */



#define SPX5_PORT_CPU          (SPX5_PORTS)  /* Next port is CPU port */

#define SPX5_PORT_CPU_0        (SPX5_PORT_CPU + 0) /* CPU Port 65 */

#define SPX5_PORT_CPU_1        (SPX5_PORT_CPU + 1) /* CPU Port 66 */

#define SPX5_PORT_VD0          (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */

#define SPX5_PORT_VD1          (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */

#define SPX5_PORT_VD2          (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/



#define PGID_BASE              SPX5_PORTS /* Starts after port PGIDs */

#define PGID_UC_FLOOD          (PGID_BASE + 0)

#define PGID_MC_FLOOD          (PGID_BASE + 1)

#define PGID_IPV4_MC_DATA      (PGID_BASE + 2)

#define PGID_IPV4_MC_CTRL      (PGID_BASE + 3)

#define PGID_IPV6_MC_DATA      (PGID_BASE + 4)

#define PGID_IPV6_MC_CTRL      (PGID_BASE + 5)

#define PGID_BCAST	       (PGID_BASE + 6)

#define PGID_CPU	       (PGID_BASE + 7)

#define PGID_MCAST_START       (PGID_BASE + 8)

#define SPX5_PORT_CPU_0        0 /* CPU Port 0 */

#define SPX5_PORT_CPU_1        1 /* CPU Port 1 */

#define SPX5_PORT_VD0          2 /* VD0/Port used for IPMC */

#define SPX5_PORT_VD1          3 /* VD1/Port used for AFI/OAM */

#define SPX5_PORT_VD2          4 /* VD2/Port used for IPinIP*/



#define PGID_UC_FLOOD          0

#define PGID_MC_FLOOD          1

#define PGID_IPV4_MC_DATA      2

#define PGID_IPV4_MC_CTRL      3

#define PGID_IPV6_MC_DATA      4

#define PGID_IPV6_MC_CTRL      5

#define PGID_BCAST             6

#define PGID_CPU               7

#define PGID_MCAST_START       8



#define PGID_TABLE_SIZE	       3290
@@ -500,6 +498,7 @@ enum sparx5_pgid_type { 
void sparx5_pgid_init(struct sparx5 *spx5);

int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx);

int sparx5_pgid_free(struct sparx5 *spx5, u16 idx);

int sparx5_get_pgid(struct sparx5 *sparx5, int pgid);



/* sparx5_pool.c */

struct sparx5_pool_entry {
@@ -516,6 +515,7 @@ int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 
/* sparx5_port.c */

int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port,

			struct sparx5_port_config *conf);

int sparx5_get_internal_port(struct sparx5 *sparx5, int port);



/* sparx5_sdlb.c */

#define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF