Unverified Commit 8ce9a2ed authored by Prajna Rajendra Kumar's avatar Prajna Rajendra Kumar Committed by Mark Brown
Browse files

spi: dt-binding: document Microchip CoreSPI 



Add device tree bindings for Microchip's CoreSPI controller.

CoreSPI is a "soft" IP core intended for FPGA implementations. Its
configurations are set in Libero. These properties represent
non-discoverable configurations determined by Verilog parameters to the
IP.

Signed-off-by: default avatarPrajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-3-prajna.rajendrakumar@microchip.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 71c814e9

Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml

+68 −2
Original line number Diff line number Diff line
@@ -21,11 +21,13 @@ properties: 
              - microchip,mpfs-qspi

              - microchip,pic64gx-qspi

          - const: microchip,coreqspi-rtl-v2

      - const: microchip,coreqspi-rtl-v2 # FPGA QSPI

      - enum:

          - microchip,coreqspi-rtl-v2 # FPGA QSPI

          - microchip,corespi-rtl-v5 # FPGA CoreSPI

          - microchip,mpfs-spi

      - items:

          - const: microchip,pic64gx-spi

          - const: microchip,mpfs-spi

      - const: microchip,mpfs-spi



  reg:

    maxItems: 1
@@ -39,6 +41,45 @@ properties: 
  clocks:

    maxItems: 1



  microchip,apb-datawidth:

    description: APB bus data width in bits.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [8, 16, 32]

    default: 8



  microchip,frame-size:

    description: |

      Number of bits per SPI frame, as configured in Libero.

      In Motorola and TI modes, this corresponds directly

      to the requested frame size. For NSC mode this is set

      to 9 + the required data frame size.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 4

    maximum: 32

    default: 8



  microchip,protocol-configuration:

    description: CoreSPI protocol selection. Determines operating mode

    $ref: /schemas/types.yaml#/definitions/string

    enum:

      - motorola

      - ti

      - nsc

    default: motorola



  microchip,motorola-mode:

    description: Motorola SPI mode selection

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2, 3]

    default: 3



  microchip,ssel-active:

    description: |

      Keep SSEL asserted between frames when using the Motorola protocol.

      When present, the controller keeps SSEL active across contiguous

      transfers and deasserts only when the overall transfer completes.

    type: boolean



required:

  - compatible

  - reg
@@ -71,6 +112,31 @@ allOf: 
        num-cs:

          maximum: 1



  - if:

      properties:

        compatible:

          contains:

            const: microchip,corespi-rtl-v5

    then:

      properties:

        num-cs:

          minimum: 1

          maximum: 8

          default: 8



        fifo-depth:

          minimum: 1

          maximum: 32

          default: 4



    else:

      properties:

        microchip,apb-datawidth: false

        microchip,frame-size: false

        microchip,protocol-configuration: false

        microchip,motorola-mode: false

        microchip,ssel-active: false



unevaluatedProperties: false



examples: