Commit 8d27dd0b authored by Dave Jiang's avatar Dave Jiang
Browse files

cxl: Clarify comment in spa_maps_hpa() 



Update the comment in spa_maps_hpa() to clearly convey the construction
of extended linear cache.

Suggested-by: default avatarDan Williams <dan.j.williams@intel.com>
Link: https://lore.kernel.org/linux-cxl/68eea19c7e67e_2f899100a8@dwillia2-mobl4.notmuch/


Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: default avatarGregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20251106170108.1468304-3-dave.jiang@intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent c43521b9

drivers/cxl/core/region.c

+3 −3
Original line number Diff line number Diff line
@@ -851,9 +851,9 @@ static bool spa_maps_hpa(const struct cxl_region_params *p, 
		return false;



	/*

	 * If an extended linear cache region then the CXL range is assumed

	 * to be fronted by the DRAM range in current known implementation.

	 * This assumption will be made until a variant implementation exists.

	 * The extended linear cache region is constructed by a 1:1 ratio

	 * where the SPA maps equal amounts of DRAM and CXL HPA capacity with

	 * CXL decoders at the high end of the SPA range.

	 */

	return p->res->start + p->cache_size == range->start &&

		p->res->end == range->end;