Commit 8d3b5f63 authored by Ivaylo Ivanov's avatar Ivaylo Ivanov Committed by Vinod Koul
Browse files

phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory 



As not only Qualcomm, but also Samsung is using the Synopsys eUSB2 IP
(albeit with a different register layout) in their newer SoCs, move the
driver out of its vendor sub-directory and rename it to phy-snps-eusb2.

Suggested-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarIvaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250504144527.1723980-4-ivo.ivanov.ivanov1@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e4c9a7b4

drivers/phy/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -43,6 +43,14 @@ config PHY_PISTACHIO_USB 
	help

	  Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.



config PHY_SNPS_EUSB2

	tristate "SNPS eUSB2 PHY Driver"

	depends on OF && (ARCH_QCOM || COMPILE_TEST)

	select GENERIC_PHY

	help

	  Enable support for the USB high-speed SNPS eUSB2 phy on select

	  SoCs. The PHY is usually paired with a Synopsys DWC3 USB controller.



config PHY_XGENE

	tristate "APM X-Gene 15Gbps PHY support"

	depends on HAS_IOMEM && OF && (ARCH_XGENE || COMPILE_TEST)

drivers/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o 
obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o

obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o

obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o

obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o

drivers/phy/qualcomm/Kconfig

+0 −9
Original line number Diff line number Diff line
@@ -125,15 +125,6 @@ config PHY_QCOM_QUSB2 
	  PHY which is usually paired with either the ChipIdea or Synopsys DWC3

	  USB IPs on MSM SOCs.



config PHY_QCOM_SNPS_EUSB2

	tristate "Qualcomm SNPS eUSB2 PHY Driver"

	depends on OF && (ARCH_QCOM || COMPILE_TEST)

	select GENERIC_PHY

	help

	  Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm

	  chipsets. The PHY is paired with a Synopsys DWC3 USB controller

	  on Qualcomm SOCs.



config PHY_QCOM_EUSB2_REPEATER

	tristate "Qualcomm SNPS eUSB2 Repeater Driver"

	depends on OF && (ARCH_QCOM || COMPILE_TEST)

drivers/phy/qualcomm/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o 
obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY)	+= phy-qcom-qmp-usb-legacy.o



obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o

obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2)	+= phy-qcom-snps-eusb2.o

obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER)	+= phy-qcom-eusb2-repeater.o

obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP)	+= phy-qcom-uniphy-pcie-28lp.o

obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o