Commit 8d528476 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/dp: Use consistent name for link bpp and compressed bpp 



Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.

For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp

For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp

For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)

For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-5-ankit.k.nautiyal@intel.com
parent fd279d21

drivers/gpu/drm/i915/display/intel_dp.c

+42 −42
Original line number Diff line number Diff line
@@ -740,7 +740,7 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p 
	return bits_per_pixel;

}



u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,

u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,

					u32 link_clock, u32 lane_count,

					u32 mode_clock, u32 mode_hdisplay,

					bool bigjoiner,
@@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, 
	int target_clock = mode->clock;

	int max_rate, mode_rate, max_lanes, max_link_clock;

	int max_dotclk = dev_priv->max_dotclk_freq;

	u16 dsc_max_output_bpp = 0;

	u16 dsc_max_compressed_bpp = 0;

	u8 dsc_slice_count = 0;

	enum drm_mode_status status;

	bool dsc = false, bigjoiner = false;
@@ -1191,14 +1191,14 @@ intel_dp_mode_valid(struct drm_connector *_connector, 
		 * integer value since we support only integer values of bpp.

		 */

		if (intel_dp_is_edp(intel_dp)) {

			dsc_max_output_bpp =

			dsc_max_compressed_bpp =

				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;

			dsc_slice_count =

				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,

								true);

		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {

			dsc_max_output_bpp =

				intel_dp_dsc_get_output_bpp(dev_priv,

			dsc_max_compressed_bpp =

				intel_dp_dsc_get_max_compressed_bpp(dev_priv,

								    max_link_clock,

								    max_lanes,

								    target_clock,
@@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, 
							     bigjoiner);

		}



		dsc = dsc_max_output_bpp && dsc_slice_count;

		dsc = dsc_max_compressed_bpp && dsc_slice_count;

	}



	/*
@@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 
	int mode_rate, link_rate, link_avail;



	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {

		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);

		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);



		mode_rate = intel_dp_link_required(clock, output_bpp);

		mode_rate = intel_dp_link_required(clock, link_bpp);



		for (i = 0; i < intel_dp->num_common_rates; i++) {

			link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1733,12 +1733,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
			return -EINVAL;

		}

	} else {

		u16 dsc_max_output_bpp = 0;

		u16 dsc_max_compressed_bpp = 0;

		u8 dsc_dp_slice_count;



		if (compute_pipe_bpp) {

			dsc_max_output_bpp =

				intel_dp_dsc_get_output_bpp(dev_priv,

			dsc_max_compressed_bpp =

				intel_dp_dsc_get_max_compressed_bpp(dev_priv,

								    pipe_config->port_clock,

								    pipe_config->lane_count,

								    adjusted_mode->crtc_clock,
@@ -1747,7 +1747,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
								    pipe_config->output_format,

								    pipe_bpp,

								    timeslots);

			if (!dsc_max_output_bpp) {

			if (!dsc_max_compressed_bpp) {

				drm_dbg_kms(&dev_priv->drm,

					    "Compressed BPP not supported\n");

				return -EINVAL;
@@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 
							     pipe_config->pipe_bpp);



			pipe_config->dsc.compressed_bpp = min_t(u16,

								dsc_max_output_bpp >> 4,

								dsc_max_compressed_bpp >> 4,

								output_bpp);

		}

		pipe_config->dsc.slice_count = dsc_dp_slice_count;
@@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector, 
static void

intel_dp_drrs_compute_config(struct intel_connector *connector,

			     struct intel_crtc_state *pipe_config,

			     int output_bpp)

			     int link_bpp)

{

	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	const struct drm_display_mode *downclock_mode =
@@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, 
	if (pipe_config->splitter.enable)

		pixel_clock /= pipe_config->splitter.link_count;



	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,

	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,

			       pipe_config->port_clock, &pipe_config->dp_m2_n2,

			       pipe_config->fec_enable);
@@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	const struct drm_display_mode *fixed_mode;

	struct intel_connector *connector = intel_dp->attached_connector;

	int ret = 0, output_bpp;

	int ret = 0, link_bpp;



	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)

		pipe_config->has_pch_encoder = true;
@@ -2324,9 +2324,9 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
		intel_dp_limited_color_range(pipe_config, conn_state);



	if (pipe_config->dsc.compression_enable)

		output_bpp = pipe_config->dsc.compressed_bpp;

		link_bpp = pipe_config->dsc.compressed_bpp;

	else

		output_bpp = intel_dp_output_bpp(pipe_config->output_format,

		link_bpp = intel_dp_output_bpp(pipe_config->output_format,

					       pipe_config->pipe_bpp);



	if (intel_dp->mso_link_count) {
@@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 


	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);



	intel_link_compute_m_n(output_bpp,

	intel_link_compute_m_n(link_bpp,

			       pipe_config->lane_count,

			       adjusted_mode->crtc_clock,

			       pipe_config->port_clock,
@@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 


	intel_vrr_compute_config(pipe_config, conn_state);

	intel_psr_compute_config(intel_dp, pipe_config, conn_state);

	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);

	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);

	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);

	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.h

+7 −7
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, 
		       unsigned int type);

bool intel_digital_port_connected(struct intel_encoder *encoder);

int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);

u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,

u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,

					u32 link_clock, u32 lane_count,

					u32 mode_clock, u32 mode_hdisplay,

					bool bigjoiner,

drivers/gpu/drm/i915/display/intel_dp_mst.c

+11 −11
Original line number Diff line number Diff line
@@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 
	int max_rate, mode_rate, max_lanes, max_link_clock;

	int ret;

	bool dsc = false, bigjoiner = false;

	u16 dsc_max_output_bpp = 0;

	u16 dsc_max_compressed_bpp = 0;

	u8 dsc_slice_count = 0;

	int target_clock = mode->clock;
@@ -969,8 +969,8 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 
		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);



		if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {

			dsc_max_output_bpp =

				intel_dp_dsc_get_output_bpp(dev_priv,

			dsc_max_compressed_bpp =

				intel_dp_dsc_get_max_compressed_bpp(dev_priv,

								    max_link_clock,

								    max_lanes,

								    target_clock,
@@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 
							     bigjoiner);

		}



		dsc = dsc_max_output_bpp && dsc_slice_count;

		dsc = dsc_max_compressed_bpp && dsc_slice_count;

	}



	/*