Commit 8d5fb297 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Split out cache status bits per-CPU family. 



Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 5a668651

include/asm-sh/cache.h

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#include <linux/init.h>

#include <asm/cpu/cache.h>



#define SH_CACHE_VALID		1

#define SH_CACHE_UPDATED	2

#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



#define __read_mostly __attribute__((__section__(".data.read_mostly")))

include/asm-sh/cpu-sh2/cache.h

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@@ -12,6 +12,11 @@ 


#define L1_CACHE_SHIFT	4



#define SH_CACHE_VALID		1

#define SH_CACHE_UPDATED	2

#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#if defined(CONFIG_CPU_SUBTYPE_SH7619)

#define CCR1		0xffffffec

#define CCR		CCR1

include/asm-sh/cpu-sh2a/cache.h

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@@ -12,6 +12,11 @@ 


#define L1_CACHE_SHIFT	4



#define SH_CACHE_VALID		1

#define SH_CACHE_UPDATED	2

#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR1		0xfffc1000

#define CCR2		0xfffc1004

include/asm-sh/cpu-sh3/cache.h

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@@ -12,6 +12,11 @@ 


#define L1_CACHE_SHIFT	4



#define SH_CACHE_VALID		1

#define SH_CACHE_UPDATED	2

#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR		0xffffffec	/* Address of Cache Control Register */



#define CCR_CACHE_CE	0x01	/* Cache Enable */

include/asm-sh/cpu-sh4/cache.h

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@@ -12,6 +12,11 @@ 


#define L1_CACHE_SHIFT	5



#define SH_CACHE_VALID		1

#define SH_CACHE_UPDATED	2

#define SH_CACHE_COMBINED	4

#define SH_CACHE_ASSOC		8



#define CCR		0xff00001c	/* Address of Cache Control Register */

#define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */

#define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/