Commit 8d94a744 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'add-rds-ptp-library-for-microchip-phys' 

Divya Koppera says:

====================
Add rds ptp library for Microchip phys

Adds support for rds ptp library in Microchip phys, where rds is internal
code name for ptp IP or hardware. This library will be re-used in
Microchip phys where same ptp hardware is used. Register base addresses
and mmd may changes, due to which base addresses and mmd is made variable
in this library.
====================

Link: https://patch.msgid.link/20241219123311.30213-1-divya.koppera@microchip.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents b4cbbf07 9fc3d6fe

drivers/net/phy/Kconfig

+8 −1
Original line number Diff line number Diff line
@@ -287,8 +287,15 @@ config MICROCHIP_PHY 


config MICROCHIP_T1_PHY

	tristate "Microchip T1 PHYs"

	select MICROCHIP_PHY_RDS_PTP if NETWORK_PHY_TIMESTAMPING && \

				  PTP_1588_CLOCK_OPTIONAL

	help

	  Supports the LAN87XX PHYs.

	  Supports the LAN8XXX PHYs.



config MICROCHIP_PHY_RDS_PTP

	tristate

	help

	  Currently supports LAN887X T1 PHY



config MICROSEMI_PHY

	tristate "Microsemi PHYs"

drivers/net/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o 
obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o

obj-$(CONFIG_MICREL_PHY)	+= micrel.o

obj-$(CONFIG_MICROCHIP_PHY)	+= microchip.o

obj-$(CONFIG_MICROCHIP_PHY_RDS_PTP)	+= microchip_rds_ptp.o

obj-$(CONFIG_MICROCHIP_T1_PHY)	+= microchip_t1.o

obj-$(CONFIG_MICROCHIP_T1S_PHY) += microchip_t1s.o

obj-$(CONFIG_MICROSEMI_PHY)	+= mscc/

drivers/net/phy/microchip_rds_ptp.c

0 → 100644
+1039 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/phy/microchip_rds_ptp.h

0 → 100644
+223 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0

 * Copyright (C) 2024 Microchip Technology

 */



#ifndef _MICROCHIP_RDS_PTP_H

#define _MICROCHIP_RDS_PTP_H



#include <linux/ptp_clock_kernel.h>

#include <linux/ptp_clock.h>

#include <linux/ptp_classify.h>

#include <linux/net_tstamp.h>

#include <linux/mii.h>

#include <linux/phy.h>



#define MCHP_RDS_PTP_CMD_CTL			0x0

#define MCHP_RDS_PTP_CMD_CTL_LTC_STEP_NSEC	BIT(6)

#define MCHP_RDS_PTP_CMD_CTL_LTC_STEP_SEC	BIT(5)

#define MCHP_RDS_PTP_CMD_CTL_CLOCK_LOAD		BIT(4)

#define MCHP_RDS_PTP_CMD_CTL_CLOCK_READ		BIT(3)

#define MCHP_RDS_PTP_CMD_CTL_EN			BIT(1)

#define MCHP_RDS_PTP_CMD_CTL_DIS		BIT(0)



#define MCHP_RDS_PTP_REF_CLK_CFG		0x2

#define MCHP_RDS_PTP_REF_CLK_SRC_250MHZ		0x0

#define MCHP_RDS_PTP_REF_CLK_PERIOD_OVERRIDE	BIT(9)

#define MCHP_RDS_PTP_REF_CLK_PERIOD		4

#define MCHP_RDS_PTP_REF_CLK_CFG_SET	(MCHP_RDS_PTP_REF_CLK_SRC_250MHZ |\

					 MCHP_RDS_PTP_REF_CLK_PERIOD_OVERRIDE |\

					 MCHP_RDS_PTP_REF_CLK_PERIOD)



#define MCHP_RDS_PTP_LTC_SEC_HI			0x5

#define MCHP_RDS_PTP_LTC_SEC_MID		0x6

#define MCHP_RDS_PTP_LTC_SEC_LO			0x7

#define MCHP_RDS_PTP_LTC_NS_HI			0x8

#define MCHP_RDS_PTP_LTC_NS_LO			0x9

#define MCHP_RDS_PTP_LTC_RATE_ADJ_HI		0xc

#define MCHP_RDS_PTP_LTC_RATE_ADJ_HI_DIR	BIT(15)

#define MCHP_RDS_PTP_LTC_RATE_ADJ_LO		0xd

#define MCHP_RDS_PTP_STEP_ADJ_HI		0x12

#define MCHP_RDS_PTP_STEP_ADJ_HI_DIR		BIT(15)

#define MCHP_RDS_PTP_STEP_ADJ_LO		0x13

#define MCHP_RDS_PTP_LTC_READ_SEC_HI		0x29

#define MCHP_RDS_PTP_LTC_READ_SEC_MID		0x2a

#define MCHP_RDS_PTP_LTC_READ_SEC_LO		0x2b

#define MCHP_RDS_PTP_LTC_READ_NS_HI		0x2c

#define MCHP_RDS_PTP_LTC_READ_NS_LO		0x2d

#define MCHP_RDS_PTP_OP_MODE			0x41

#define MCHP_RDS_PTP_OP_MODE_DIS		0

#define MCHP_RDS_PTP_OP_MODE_STANDALONE		1

#define MCHP_RDS_PTP_LATENCY_CORRECTION_CTL	0x44

#define MCHP_RDS_PTP_PREDICTOR_EN		BIT(6)

#define MCHP_RDS_PTP_TX_PRED_DIS		BIT(1)

#define MCHP_RDS_PTP_RX_PRED_DIS		BIT(0)

#define MCHP_RDS_PTP_LATENCY_SETTING		(MCHP_RDS_PTP_PREDICTOR_EN | \

						 MCHP_RDS_PTP_TX_PRED_DIS | \

						 MCHP_RDS_PTP_RX_PRED_DIS)



#define MCHP_RDS_PTP_INT_EN			0x0

#define MCHP_RDS_PTP_INT_STS			0x01

#define MCHP_RDS_PTP_INT_TX_TS_OVRFL_EN		BIT(3)

#define MCHP_RDS_PTP_INT_TX_TS_EN		BIT(2)

#define MCHP_RDS_PTP_INT_RX_TS_OVRFL_EN		BIT(1)

#define MCHP_RDS_PTP_INT_RX_TS_EN		BIT(0)

#define MCHP_RDS_PTP_INT_ALL_MSK	(MCHP_RDS_PTP_INT_TX_TS_OVRFL_EN | \

					 MCHP_RDS_PTP_INT_TX_TS_EN | \

					 MCHP_RDS_PTP_INT_RX_TS_OVRFL_EN |\

					 MCHP_RDS_PTP_INT_RX_TS_EN)



#define MCHP_RDS_PTP_CAP_INFO			0x2e

#define MCHP_RDS_PTP_TX_TS_CNT(v)		(((v) & GENMASK(11, 8)) >> 8)

#define MCHP_RDS_PTP_RX_TS_CNT(v)		((v) & GENMASK(3, 0))



#define MCHP_RDS_PTP_RX_PARSE_CONFIG		0x42

#define MCHP_RDS_PTP_RX_PARSE_L2_ADDR_EN	0x44

#define MCHP_RDS_PTP_RX_PARSE_IPV4_ADDR_EN	0x45



#define MCHP_RDS_PTP_RX_TIMESTAMP_CONFIG	0x4e

#define MCHP_RDS_PTP_RX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0)



#define MCHP_RDS_PTP_RX_VERSION			0x48

#define MCHP_RDS_PTP_RX_TIMESTAMP_EN		0x4d



#define MCHP_RDS_PTP_RX_INGRESS_NS_HI		0x54

#define MCHP_RDS_PTP_RX_INGRESS_NS_HI_TS_VALID	BIT(15)



#define MCHP_RDS_PTP_RX_INGRESS_NS_LO		0x55

#define MCHP_RDS_PTP_RX_INGRESS_SEC_HI		0x56

#define MCHP_RDS_PTP_RX_INGRESS_SEC_LO		0x57

#define MCHP_RDS_PTP_RX_MSG_HDR2		0x59



#define MCHP_RDS_PTP_TX_PARSE_CONFIG		0x82

#define MCHP_RDS_PTP_PARSE_CONFIG_LAYER2_EN	BIT(0)

#define MCHP_RDS_PTP_PARSE_CONFIG_IPV4_EN	BIT(1)

#define MCHP_RDS_PTP_PARSE_CONFIG_IPV6_EN	BIT(2)



#define MCHP_RDS_PTP_TX_PARSE_L2_ADDR_EN	0x84

#define MCHP_RDS_PTP_TX_PARSE_IPV4_ADDR_EN	0x85



#define MCHP_RDS_PTP_TX_VERSION			0x88

#define MCHP_RDS_PTP_MAX_VERSION(x)		(((x) & GENMASK(7, 0)) << 8)

#define MCHP_RDS_PTP_MIN_VERSION(x)		((x) & GENMASK(7, 0))



#define MCHP_RDS_PTP_TX_TIMESTAMP_EN		0x8d

#define MCHP_RDS_PTP_TIMESTAMP_EN_SYNC		BIT(0)

#define MCHP_RDS_PTP_TIMESTAMP_EN_DREQ		BIT(1)

#define MCHP_RDS_PTP_TIMESTAMP_EN_PDREQ		BIT(2)

#define MCHP_RDS_PTP_TIMESTAMP_EN_PDRES		BIT(3)

#define MCHP_RDS_PTP_TIMESTAMP_EN_ALL	(MCHP_RDS_PTP_TIMESTAMP_EN_SYNC |\

					 MCHP_RDS_PTP_TIMESTAMP_EN_DREQ |\

					 MCHP_RDS_PTP_TIMESTAMP_EN_PDREQ |\

					 MCHP_RDS_PTP_TIMESTAMP_EN_PDRES)



#define MCHP_RDS_PTP_TX_TIMESTAMP_CONFIG	0x8e

#define MCHP_RDS_PTP_TX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0)



#define MCHP_RDS_PTP_TX_MOD			0x8f

#define MCHP_RDS_TX_MOD_PTP_SYNC_TS_INSERT	BIT(12)



#define MCHP_RDS_PTP_TX_EGRESS_NS_HI		0x94

#define MCHP_RDS_PTP_TX_EGRESS_NS_HI_TS_VALID	BIT(15)



#define MCHP_RDS_PTP_TX_EGRESS_NS_LO		0x95

#define MCHP_RDS_PTP_TX_EGRESS_SEC_HI		0x96

#define MCHP_RDS_PTP_TX_EGRESS_SEC_LO		0x97

#define MCHP_RDS_PTP_TX_MSG_HDR2		0x99



#define MCHP_RDS_PTP_TSU_GEN_CONFIG		0xc0

#define MCHP_RDS_PTP_TSU_GEN_CFG_TSU_EN		BIT(0)



#define MCHP_RDS_PTP_TSU_HARD_RESET		0xc1

#define MCHP_RDS_PTP_TSU_HARDRESET		BIT(0)



/* Represents 1ppm adjustment in 2^32 format with

 * each nsec contains 4 clock cycles in 250MHz.

 * The value is calculated as following: (1/1000000)/((2^-32)/4)

 */

#define MCHP_RDS_PTP_1PPM_FORMAT		17179

#define MCHP_RDS_PTP_FIFO_SIZE			8

#define MCHP_RDS_PTP_MAX_ADJ			31249999



#define BASE_CLK(p)				((p)->clk_base_addr)

#define BASE_PORT(p)				((p)->port_base_addr)

#define PTP_MMD(p)				((p)->mmd)



enum mchp_rds_ptp_base {

	MCHP_RDS_PTP_PORT,

	MCHP_RDS_PTP_CLOCK

};



enum mchp_rds_ptp_fifo_dir {

	MCHP_RDS_PTP_INGRESS_FIFO,

	MCHP_RDS_PTP_EGRESS_FIFO

};



struct mchp_rds_ptp_clock {

	struct mii_timestamper mii_ts;

	struct phy_device *phydev;

	struct ptp_clock *ptp_clock;



	struct sk_buff_head tx_queue;

	struct sk_buff_head rx_queue;

	struct list_head rx_ts_list;



	struct ptp_clock_info caps;



	/* Lock for Rx ts fifo */

	spinlock_t rx_ts_lock;

	int hwts_tx_type;



	enum hwtstamp_rx_filters rx_filter;

	int layer;

	int version;

	u16 port_base_addr;

	u16 clk_base_addr;



	/* Lock for phc */

	struct mutex ptp_lock;

	u8 mmd;

};



struct mchp_rds_ptp_rx_ts {

	struct list_head list;

	u32 seconds;

	u32 nsec;

	u16 seq_id;

};



#if IS_ENABLED(CONFIG_MICROCHIP_PHY_RDS_PTP)



struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd,

					      u16 clk_base, u16 port_base);



int mchp_rds_ptp_top_config_intr(struct mchp_rds_ptp_clock *clock,

				 u16 reg, u16 val, bool enable);



irqreturn_t mchp_rds_ptp_handle_interrupt(struct mchp_rds_ptp_clock *clock);



#else



static inline struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device

							    *phydev, u8 mmd,

							    u16 clk_base,

							    u16 port_base)

{

	return NULL;

}



static inline int mchp_rds_ptp_top_config_intr(struct mchp_rds_ptp_clock *clock,

					       u16 reg, u16 val, bool enable)

{

	return 0;

}



static inline irqreturn_t mchp_rds_ptp_handle_interrupt(struct

							mchp_rds_ptp_clock

							* clock)

{

	return IRQ_NONE;

}



#endif //CONFIG_MICROCHIP_PHY_RDS_PTP



#endif //_MICROCHIP_RDS_PTP_H

drivers/net/phy/microchip_t1.c

+38 −3
Original line number Diff line number Diff line
@@ -10,11 +10,15 @@ 
#include <linux/ethtool.h>

#include <linux/ethtool_netlink.h>

#include <linux/bitfield.h>

#include "microchip_rds_ptp.h"



#define PHY_ID_LAN87XX				0x0007c150

#define PHY_ID_LAN937X				0x0007c180

#define PHY_ID_LAN887X				0x0007c1f0



#define MCHP_RDS_PTP_LTC_BASE_ADDR		0xe000

#define MCHP_RDS_PTP_PORT_BASE_ADDR	    (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)



/* External Register Control Register */

#define LAN87XX_EXT_REG_CTL                     (0x14)

#define LAN87XX_EXT_REG_CTL_RD_CTL              (0x1000)
@@ -229,6 +233,7 @@ 


#define LAN887X_INT_STS				0xf000

#define LAN887X_INT_MSK				0xf001

#define LAN887X_INT_MSK_P1588_MOD_INT_MSK	BIT(3)

#define LAN887X_INT_MSK_T1_PHY_INT_MSK		BIT(2)

#define LAN887X_INT_MSK_LINK_UP_MSK		BIT(1)

#define LAN887X_INT_MSK_LINK_DOWN_MSK		BIT(0)
@@ -319,6 +324,8 @@ struct lan887x_regwr_map { 


struct lan887x_priv {

	u64 stats[ARRAY_SIZE(lan887x_hw_stats)];

	struct mchp_rds_ptp_clock *clock;

	bool init_done;

};



static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
@@ -1269,8 +1276,19 @@ static int lan887x_get_features(struct phy_device *phydev) 


static int lan887x_phy_init(struct phy_device *phydev)

{

	struct lan887x_priv *priv = phydev->priv;

	int ret;



	if (!priv->init_done && phy_interrupt_is_valid(phydev)) {

		priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1,

						 MCHP_RDS_PTP_LTC_BASE_ADDR,

						 MCHP_RDS_PTP_PORT_BASE_ADDR);

		if (IS_ERR(priv->clock))

			return PTR_ERR(priv->clock);



		priv->init_done = true;

	}



	/* Clear loopback */

	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,

				 LAN887X_MIS_CFG_REG2,
@@ -1470,6 +1488,7 @@ static int lan887x_probe(struct phy_device *phydev) 
	if (!priv)

		return -ENOMEM;



	priv->init_done = false;

	phydev->priv = priv;



	return lan887x_phy_setup(phydev);
@@ -1518,6 +1537,7 @@ static void lan887x_get_strings(struct phy_device *phydev, u8 *data) 


static int lan887x_config_intr(struct phy_device *phydev)

{

	struct lan887x_priv *priv = phydev->priv;

	int rc;



	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
@@ -1537,12 +1557,24 @@ static int lan887x_config_intr(struct phy_device *phydev) 


		rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);

	}

	if (rc < 0)

		return rc;



	return rc < 0 ? rc : 0;

	if (phy_is_default_hwtstamp(phydev)) {

		return mchp_rds_ptp_top_config_intr(priv->clock,

					LAN887X_INT_MSK,

					LAN887X_INT_MSK_P1588_MOD_INT_MSK,

					(phydev->interrupts ==

					 PHY_INTERRUPT_ENABLED));

	}



	return 0;

}



static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev)

{

	struct lan887x_priv *priv = phydev->priv;

	int rc = IRQ_NONE;

	int irq_status;



	irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
@@ -1553,10 +1585,13 @@ static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev) 


	if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) {

		phy_trigger_machine(phydev);

		return IRQ_HANDLED;

		rc = IRQ_HANDLED;

	}



	return IRQ_NONE;

	if (irq_status & LAN887X_INT_MSK_P1588_MOD_INT_MSK)

		rc = mchp_rds_ptp_handle_interrupt(priv->clock);



	return rc;

}



static int lan887x_cd_reset(struct phy_device *phydev,