Commit 8d9b9d98 authored by Wei-Lin Chang's avatar Wei-Lin Chang Committed by Marc Zyngier
Browse files

KVM: arm64: nv: Consider the DS bit when translating TCR_EL2 



When running an nVHE L1, TCR_EL2 is mapped to TCR_EL1. Writes to the
register are trapped and written to TCR_EL1 after a translation.
Booting an nVHE L1 with 52-bit VA isn't working because the translation
was ignoring the DS bit set by the guest, hence causing repeating level
0 faults. Add it in the translation function.

Signed-off-by: default avatarWei-Lin Chang <weilin.chang@arm.com>
Link: https://patch.msgid.link/20260505144735.1496530-1-weilin.chang@arm.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 1f7305d8

arch/arm64/include/asm/kvm_nested.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2) 
static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr)

{

	return TCR_EPD1_MASK |				/* disable TTBR1_EL1 */

	       ((tcr & TCR_EL2_DS) ? TCR_DS : 0) |

	       ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) |

	       tcr_el2_ps_to_tcr_el1_ips(tcr) |

	       (tcr & TCR_EL2_TG0_MASK) |