Commit 8de397a5 authored by Jie Zhang's avatar Jie Zhang Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: talos: Add gpu and rgmu nodes 



Add gpu and rgmu nodes for Talos chipset.

Signed-off-by: default avatarJie Zhang <quic_jiezh@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312-qcs615-spin-2-v8-2-fca38edcd6e6@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 1d5c82f1

arch/arm64/boot/dts/qcom/talos.dtsi

+110 −0
Original line number Diff line number Diff line
@@ -651,6 +651,11 @@ rproc_adsp_mem: rproc-adsp@95900000 { 
			reg = <0x0 0x95900000 0x0 0x1e00000>;

			no-map;

		};



		pil_gpu_mem: pil-gpu@97715000 {

			reg = <0x0 0x97715000 0x0 0x2000>;

			no-map;

		};

	};



	soc: soc@0 {
@@ -1833,6 +1838,111 @@ data-pins { 
			};

		};



		gpu: gpu@5000000 {

			compatible = "qcom,adreno-612.0", "qcom,adreno";

			reg = <0x0 0x05000000 0x0 0x40000>,

			      <0x0 0x0509e000 0x0 0x1000>,

			      <0x0 0x05061000 0x0 0x800>;

			reg-names = "kgsl_3d0_reg_memory",

				    "cx_mem",

				    "cx_dbgc";



			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;

			clock-names = "core";



			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;



			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "gfx-mem";



			iommus = <&adreno_smmu 0x0 0x401>;



			operating-points-v2 = <&gpu_opp_table>;

			power-domains = <&rpmhpd RPMHPD_CX>;



			qcom,gmu = <&gmu>;



			#cooling-cells = <2>;



			status = "disabled";



			gpu_zap_shader: zap-shader {

				memory-region = <&pil_gpu_mem>;

			};



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-845000000 {

					opp-hz = /bits/ 64 <845000000>;

					required-opps = <&rpmhpd_opp_turbo>;

					opp-peak-kBps = <7050000>;

				};



				opp-745000000 {

					opp-hz = /bits/ 64 <745000000>;

					required-opps = <&rpmhpd_opp_nom_l1>;

					opp-peak-kBps = <6075000>;

				};



				opp-650000000 {

					opp-hz = /bits/ 64 <650000000>;

					required-opps = <&rpmhpd_opp_nom>;

					opp-peak-kBps = <5287500>;

				};



				opp-500000000 {

					opp-hz = /bits/ 64 <500000000>;

					required-opps = <&rpmhpd_opp_svs_l1>;

					opp-peak-kBps = <3975000>;

				};



				opp-435000000 {

					opp-hz = /bits/ 64 <435000000>;

					required-opps = <&rpmhpd_opp_svs>;

					opp-peak-kBps = <3000000>;

				};

			};

		};



		gmu: gmu@506a000 {

			compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";

			reg = <0x0 0x0506d000 0x0 0x2c000>;



			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_CXO_CLK>,

				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

			clock-names = "gmu",

				      "cxo",

				      "axi",

				      "memnoc",

				      "smmu_vote";



			power-domains = <&gpucc CX_GDSC>,

					<&gpucc GX_GDSC>;

			power-domain-names = "cx",

					     "gx";



			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;

			interrupt-names = "oob",

					  "gmu";



			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					required-opps = <&rpmhpd_opp_low_svs>;

				};

			};

		};



		gpucc: clock-controller@5090000 {

			compatible = "qcom,qcs615-gpucc";

			reg = <0 0x05090000 0 0x9000>;