Commit 8dfce5f3 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up some DISPLAY_VER checks 



Use the >= and < operators for the DISPLAY_VER checks everywhere.
This is what most of the code does, but especially recently random
pieces of code have started doing this differently for no good reason.

Conversion done with the following cocci:
@find@
expression i915;
constant ver;
@@
(
DISPLAY_VER(i915) <= ver
|
DISPLAY_VER(i915) > ver
)

@script:python inc@
old_ver << find.ver;
new_ver;
@@
coccinelle.new_ver = str(int(old_ver) + 1)

@@
expression find.i915;
constant find.ver;
identifier inc.new_ver;
@@
(
- DISPLAY_VER(i915) <= ver
+ DISPLAY_VER(i915) < new_ver
|
- DISPLAY_VER(i915) > ver
+ DISPLAY_VER(i915) >= new_ver
)

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231127145028.4899-4-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 9c058492

drivers/gpu/drm/i915/display/i9xx_wm.c

+4 −4
Original line number Diff line number Diff line
@@ -2477,7 +2477,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, 
		 * FIFO size is only half of the self

		 * refresh FIFO size on ILK/SNB.

		 */

		if (DISPLAY_VER(dev_priv) <= 6)

		if (DISPLAY_VER(dev_priv) < 7)

			fifo_size /= 2;

	}
@@ -2818,7 +2818,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state, 
	usable_level = dev_priv->display.wm.num_levels - 1;



	/* ILK/SNB: LP2+ watermarks only w/o sprites */

	if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)

	if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)

		usable_level = 1;



	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -2961,7 +2961,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, 
	int last_enabled_level = num_levels - 1;



	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */

	if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&

	if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&

	    config->num_pipes_active > 1)

		last_enabled_level = 0;
@@ -3060,7 +3060,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, 
		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the

		 * level is disabled. Doing otherwise could cause underruns.

		 */

		if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {

		if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {

			drm_WARN_ON(&dev_priv->drm, wm_lp != 1);

			results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;

		}

drivers/gpu/drm/i915/display/intel_bw.c

+4 −3
Original line number Diff line number Diff line
@@ -87,7 +87,8 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 
		return ret;



	dclk = val & 0xffff;

	sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);

	sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),

				1000);

	sp->t_rp = (val & 0xff0000) >> 16;

	sp->t_rcd = (val & 0xff000000) >> 24;
@@ -480,7 +481,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel 
	if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)

		qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);



	if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)

	if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)

		drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");

	if (qi.max_numchannels != 0)

		num_channels = min_t(u8, num_channels, qi.max_numchannels);
@@ -897,7 +898,7 @@ static int icl_find_qgv_points(struct drm_i915_private *i915, 
		unsigned int idx;

		unsigned int max_data_rate;



		if (DISPLAY_VER(i915) > 11)

		if (DISPLAY_VER(i915) >= 12)

			idx = tgl_max_bw_index(i915, num_active_planes, i);

		else

			idx = icl_max_bw_index(i915, num_active_planes, i);

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −1
Original line number Diff line number Diff line
@@ -2597,7 +2597,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 
		 * Since PPC = 2 with bigjoiner

		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits

		 */

		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;

		int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;

		int min_cdclk_bj =

			(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *

			 pixel_clock) / (2 * bigjoiner_interface_bits);

drivers/gpu/drm/i915/display/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -2627,7 +2627,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta 
		crtc_vblank_start = 1;

	}



	if (DISPLAY_VER(dev_priv) > 3)

	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),

			       vsyncshift);
@@ -3167,7 +3167,7 @@ static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 
		break;

	case 36:

		/* Port output 12BPC defined for ADLP+ */

		if (DISPLAY_VER(dev_priv) > 12)

		if (DISPLAY_VER(dev_priv) >= 13)

			val |= PIPE_MISC_BPC_12_ADLP;

		break;

	default:
@@ -3224,7 +3224,7 @@ int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 
	 * MIPI DSI HW readout.

	 */

	case PIPE_MISC_BPC_12_ADLP:

		if (DISPLAY_VER(dev_priv) > 12)

		if (DISPLAY_VER(dev_priv) >= 13)

			return 36;

		fallthrough;

	default:
@@ -7763,7 +7763,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de 
	 * Cantiga+ cannot handle modes with a hsync front porch of 0.

	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.

	 */

	if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&

	if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&

	    mode->hsync_start == mode->hdisplay)

		return MODE_H_ILLEGAL;

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ struct drm_printer; 
#define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)

#define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)

#define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)

#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) > 2)

#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)

#define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) >= 4)

#define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))

#define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)