Commit 8e05ce69 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-j784s4-main: Add PCIe nodes 



TI's J784S4 SoC has four instances of Gen3 PCIe Controllers namely
PCIe0, PCIe1, PCIe2 and PCIe3. PCIe0 and PCIe1 are 4-Lane controllers
while PCIe2 and PCIe3 are 2-Lane controllers.

Add support for the Root Complex Mode of operation of these PCIe instances.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240529082259.1619695-2-s-vadapalli@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 2116f8b7

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

+136 −0
Original line number Diff line number Diff line
@@ -61,6 +61,26 @@ cpsw0_phy_gmii_sel: phy@4044 { 
			ti,qsgmii-main-ports = <7>, <7>;

		};



		pcie0_ctrl: pcie0-ctrl@4070 {

			compatible = "ti,j784s4-pcie-ctrl", "syscon";

			reg = <0x4070 0x4>;

		};



		pcie1_ctrl: pcie1-ctrl@4074 {

			compatible = "ti,j784s4-pcie-ctrl", "syscon";

			reg = <0x4074 0x4>;

		};



		pcie2_ctrl: pcie2-ctrl@4078 {

			compatible = "ti,j784s4-pcie-ctrl", "syscon";

			reg = <0x4078 0x4>;

		};



		pcie3_ctrl: pcie3-ctrl@407c {

			compatible = "ti,j784s4-pcie-ctrl", "syscon";

			reg = <0x407c 0x4>;

		};



		serdes_ln_ctrl: mux-controller@4080 {

			compatible = "reg-mux";

			reg = <0x00004080 0x30>;
@@ -959,6 +979,122 @@ main_sdhci1: mmc@4fb0000 { 
		status = "disabled";

	};



	pcie0_rc: pcie@2900000 {

		compatible = "ti,j784s4-pcie-host";

		reg = <0x00 0x02900000 0x00 0x1000>,

		      <0x00 0x02907000 0x00 0x400>,

		      <0x00 0x0d000000 0x00 0x00800000>,

		      <0x00 0x10000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;

		max-link-speed = <3>;

		num-lanes = <4>;

		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 332 0>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		vendor-id = <0x104c>;

		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,

			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};



	pcie1_rc: pcie@2910000 {

		compatible = "ti,j784s4-pcie-host";

		reg = <0x00 0x02910000 0x00 0x1000>,

		      <0x00 0x02917000 0x00 0x400>,

		      <0x00 0x0d800000 0x00 0x00800000>,

		      <0x00 0x18000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;

		max-link-speed = <3>;

		num-lanes = <4>;

		power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 333 0>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		vendor-id = <0x104c>;

		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x10000 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,

			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};



	pcie2_rc: pcie@2920000 {

		compatible = "ti,j784s4-pcie-host";

		reg = <0x00 0x02920000 0x00 0x1000>,

		      <0x00 0x02927000 0x00 0x400>,

		      <0x00 0x0e000000 0x00 0x00800000>,

		      <0x44 0x00000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;

		max-link-speed = <3>;

		num-lanes = <2>;

		power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 334 0>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		vendor-id = <0x104c>;

		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x20000 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,

			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};



	pcie3_rc: pcie@2930000 {

		compatible = "ti,j784s4-pcie-host";

		reg = <0x00 0x02930000 0x00 0x1000>,

		      <0x00 0x02937000 0x00 0x400>,

		      <0x00 0x0e800000 0x00 0x00800000>,

		      <0x44 0x10000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;

		max-link-speed = <3>;

		num-lanes = <2>;

		power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 335 0>;

		clock-names = "fck";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		vendor-id = <0x104c>;

		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x30000 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,

			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};



	serdes_wiz0: wiz@5060000 {

		compatible = "ti,j784s4-wiz-10g";

		#address-cells = <1>;

arch/arm64/boot/dts/ti/k3-j784s4.dtsi

+9 −1
Original line number Diff line number Diff line
@@ -238,7 +238,10 @@ cbass_main: bus@100000 { 
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */

			 <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */

			 <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */

			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/

			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/

			 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/

			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/

			 <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/

			 <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */

			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */

			 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
@@ -248,7 +251,12 @@ cbass_main: bus@100000 { 
			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */

			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */

			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */

			 <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */

			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */

			 <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */

			 <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */

			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */

			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */

			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */



			 /* MCUSS_WKUP Range */