Commit 8e11a94e authored by Mrinmay Sarkar's avatar Mrinmay Sarkar Committed by Vinod Koul
Browse files

phy: qcom-qmp-pcie: add endpoint support for sa8775p 



Add support for dual lane end point mode PHY found on sa8755p platform.

Signed-off-by: default avatarMrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f5d5a0b5

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+37 −0
Original line number Diff line number Diff line
@@ -2147,6 +2147,34 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] 
	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),

};



static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),

};



static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),

};



struct qmp_pcie_offsets {

	u16 serdes;

	u16 pcs;
@@ -3043,6 +3071,15 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 
		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),

	},



	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {

		.serdes		= sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,

		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),

		.pcs_misc	= sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),

		.pcs		= sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,

		.pcs_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),

	},



	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h

+2 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 
#ifndef QCOM_PHY_QMP_PCS_V5_20_H_

#define QCOM_PHY_QMP_PCS_V5_20_H_



#define QPHY_V5_20_PCS_INSIG_SW_CTRL7			0x060

#define QPHY_V5_20_PCS_INSIG_MX_CTRL7			0x07c

#define QPHY_V5_20_PCS_G3S2_PRE_GAIN			0x170

#define QPHY_V5_20_PCS_RX_SIGDET_LVL			0x188

#define QPHY_V5_20_PCS_EQ_CONFIG2			0x1d8